Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 Editors: F. Roozeboom
V. Narayanan
Eindhoven University of Technology, and TNO Eindhoven Eindhoven, The Netherlands
IBM T.J. Watson Research Center Yorktown Heights, New York, USA
K. Kakushima
D.-L. Kwong
Tokyo Institute of Technology Yokohama, Japan
Institute of Microelectronics Singapore
H. Iwai
E. P. Gusev
Tokyo Institute of Technology Yokohama, Japan
Qualcomm MEMS Technologies San Diego, California, USA
P. J. Timans Mattson Technology Inc. Fremont, California, USA
Sponsoring Divisions: Electronics and Photonics Dielectric Science & Technology
Published by
TM
The Electrochemical Society 65 South Main Street, Building D Pennington, NJ 08534-2839, USA tel 609 737 1902 fax 609 737 2743 www.electrochem.org
Vol. 45, No. 6
Copyright 2012 by The Electrochemical Society. All rights reserved. This book has been registered with Copyright Clearance Center. For further information, please contact the Copyright Clearance Center, Salem, Massachusetts. Published by: The Electrochemical Society 65 South Main Street Pennington, New Jersey 08534-2839, USA Telephone 609.737.1902 Fax 609.737.2743 e-mail:
[email protected] Web: www.electrochem.org ISSN 1938-6737 (online) ISSN 1938-5862 (print) ISSN 2151-2051 (cd-rom) ISBN 978-1-56677-958-6 (Hardcover) ISBN 978-1-60768-316-2 (PDF) Printed in the United States of America.
PREFACE From May 6-10, 2012, the city of Seattle (WA, USA) was the venue of the international symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 which was held as a part of the 221th Meeting of the Electrochemical Society. This symposium has its roots in the very successful annual series of symposia on Advanced Gate Stack, Source/Drain and Channel Engineering and on Advanced Thermal Processing that have been organized in the past decade. With the ongoing transition from traditional scaling in CMOS integrated circuit manufacturing (popularly More Moore) into more diversification and embedded functionality (More than Moore) and advanced nanoelectronic devices and materials (Beyond Moore) the symposium organizers have redirected and widened the scope of this technology-driven symposium into a title that is more appropriate for this decade. This symposium was the second in this new direction, and its main objective was to address the latest advances in channel, gate stack and source/drain engineering for state-of-the-art CMOS integrated circuit manufacturing, next to advanced (3D) transistor structures and new exploratory areas such as 3D integration, MEMS & NEMS devices, which are adding functionalities to conventional CMOS devices. This book contains almost all of the papers (about 30) presented at the symposium. The papers are arranged in several sections. The first section focuses on new materials and processes in nanofabrication. The book opens with the keynote address by IBM’s T. Theis covering novel low-voltage digital switch device concepts for advanced information processing. This is followed by a section on Strain Engineering, Contacts and Doping, with new developments in CVD and ALD-related processing. The next section of the proceedings covers the growing area of MEMS and NEMS, and their heterogeneous integration with CMOS in the back-end-of-line. Bonding and 3D integration are the next topic, in particular Through-Silicon Via (TSV) technology which is emerging as an enabler of heterogeneously 3D integrated multifunctional systems. The following section makes clear that advanced MOS gate stack and channel engineering continues to be an essential part in IC development with novel dielectrics for further effective oxide thickness scaling. The last section is on new FINFET transistor and nanowire structures, and on ultrathin SOI and buried oxide films to improve short channel effects.
iii
As in previous years, the organizers would like to express special thanks to all speakers, invited and contributing, for their interest in this symposium, and for submitting high-quality abstracts and preparing their manuscripts at short notice. Finally, the success of the symposium is greatly and positively influenced by the financial support given by the sponsoring ECS divisions, Electronics and Photonics (lead sponsor), Dielectric Science and Technology (co-sponsor) as well as the following industrial sponsors (at the time of printing): Air Liquide, ASM International, Centrotherm, IBM, Mattson Technology, Qualcomm, and Sigma-Aldrich. Their continued support and loyal sponsorship are highly valued, given the persisting worldwide economic constraints.
F. Roozeboom, Eindhoven University of Technology, and TNO, Eindhoven, The Netherlands V. Narayanan, IBM T J Watson Research Center Yorktown Heights, New York, USA K. Kakushima, Tokyo Institute of Technology, Yokohama, Japan D.-L. Kwong, Institute of Microelectronics, Singapore H. Iwai, Tokyo Institute of Technology, Yokohama, Japan E. P. Gusev, Qualcomm MEMS Technologies, San Jose, California, USA P. J. Timans, Mattson Technology Inc., Fremont, California, USA April 2012
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ECS Transactions, Volume 45, Issue 6 Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 2
Table of Contents Preface
iii
Chapter 1 Plenary (Keynote) In Quest of a Fast, Low-Voltage Digital Switch T. N. Theis
3
Chapter 2 Strain Engineering/Contacts/Doping (Invited) Ultrathin Ni1-xPtx Films as Electrical Contact in CMOS Devices S. Zhang
15
Characterization of Strain-Engineered Si:C Epitaxial Layers on Si Substrates W. Yoo, T. Ishigaki, T. Ueda, J. Kajiwara, K. Kang, P. Hung, K. Ang, and B. Min
23
Ultra Low-Temperature Epitaxial Growth of Strained Si Directly on Si Substrates D. Shahrjerdi, B. Hekmatshoar, S. W. Bedell, J. A. Ott, M. Hopstaken, and D. K. Sadana
31
Pattern Dependency of Pure-Boron-Layer Chemical-Vapor Depositions V. Mohammadi, W. de Boer, T. L. Scholtes, and L. K. Nanver
39
The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms during Cyclic Selective Epitaxial Growth of Silicon K. Lee, Y. Kang, H. An, S. Jeong, J. Han, B. Kim, S. Nam, H. Kang, H. Jeong, C. Chung, H. Park, and B. Choi
49
P-type Doping of Silicon Suitable for Structures with High Aspect Ratios by Using a Dopant Source of Boron Oxide Grown by Atomic Layer Deposition B. Kalkofen, V. Mothukuru, M. Lisker, and E. P. Burte
55
v
Gas Source Depletion Study of High-Order Silanes of Silicon-Based Epitaxial Layers Grown with RPCVD and Low Temperatures K. H. Chung, P. Brabant, M. Shinriki, S. Hasaka, T. Francis, H. He, and D. K. Sadana
69
Electrical and Reliability Characterization of Ti/TiN Thin Film Resistor Y. Cheng, W. Chang, B. Wei, F. Lu, and Y. Wang
81
Chapter 3 MEMS/NEMS (Invited) From MEMS-CMOS towards Heterogeneous Integration over Scale H. Fujita, H. Toshiyoshi, and T. Ishida
93
Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage I. Chen, L. Hutin, C. Park, R. Lee, R. Nathanael, J. Yaung, J. Jeon, and T. King Liu
101
(Invited) Applications of Nanowire Enabled Micro Opto-Thermal Actuation Y. Lu and A. Lal
107
Chapter 4 Bonding and 3D Integration (Invited) Advances in Materials and Processes for 3D-TSV Integration J. J. Lu
119
Ge/Si p-n Diode Fabricated by Direct Wafer Bonding and Layer Exfoliation F. Gity, K. Byun, K. Lee, K. Cherkaoui, J. M. Hayes, A. P. Morrison, C. Colinge, and B. Corbett
131
Wet-Chemical Silicon Wafer Thinning Process for High Chip Strength K. Yoshikawa, T. Miyazaki, N. Watanabe, and M. Aoyagi
141
(Invited) Scaling Requires Continuous Innovation in Thermal Processing: Low-Temperature Plasma Oxidation W. Lerch, W. Kegel, J. Niess, A. Gschwandtner, J. Gelpey, and F. Cristiano
151
Heterogeneous Chip Integration into Silicon Templates by Through-Wafer Copper Electroplating C. D. Meyer, S. S. Bedair, S. M. Trocchia, M. A. Mirabelli, W. L. Benard, T. G. Ivanov, and L. M. Boteler
163
vi
Characterization of Grobal and Local Wafer Shape Change along Through Silicon Via Process Steps C. Lee, S. Jie, S. Park, H. Yoo, I. Han, and W. Yoo
171
Chapter 5 High-k, Gate Stack and Alternate Channels (Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic R. J. Hill, J. Huang, W. Loh, T. Kim, M. H. Wong, D. Veksler, T. H. Cunningham, R. Droopad, J. Oh, C. Hobbs, P. D. Kirsch, and R. Jammy
179
Enhancement in Electron Mobility at the Interface between Gd2O3(100) and n-type Si(100) W. Sitaputra and R. Tsu
185
Heterepitaxial Growth of High Quality Germanium Layer on Si(001)for GOI Fabrication J. Bian, Z. Xue, D. Chen, Z. Di, and M. Zhang
195
Nanocrystalline MoOx Embedded ZrHfO High-k Memories - Charge Trapping and Retention Characteristics X. Liu, C. Yang, Y. Kuo, and T. Yuan
203
Electrical Improvement of MIS Capacitor with HfAlOx Gate Dielectrics Treated by Dual Plasma Treatment I. Deng, K. Chang, T. Chang, P. Chang, B. Huang, and C. Wu
211
Cauchy-Urbach Dielectric Function Modeling of Amorphous High-k LaGdO3 Films S. P. Pavunny, R. Thomas, and R. S. Katiyar
219
Chapter 6 FINFET/ETSOI/Nanowires Ultra-Thin SOI/BOX Layers and Next Generations Planar Fully Depleted Substrates W. Schwarzenbach, V. Barec, X. Cauchy, N. Daval, S. Kerdiles, F. Boedt, O. Bonnin, B. Nguyen, and C. Maleville
227
(Invited) On-Current Variability Sources of FinFETs: Analysis and Perspective for 14nm-Lg Technology T. Matsukawa, Y. Liu, K. Endo, S. O'uchi, and M. Masahara
231
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Chapter 7 Novel Devices and Processing The Effect of Plasma Treatment on Reducing Electroforming Voltage of Silicon Oxide RRAM F. Xue, Y. Chen, Y. Wang, F. Zhou, Y. Chang, B. Fowler, and J. Lee
245
Development of High Selectivity Phosphoric Acid and its Application to Flash STI Pattern S. Cho, Y. Lee, J. Han, H. Park, H. Kim, S. Kwak, K. Yang, K. Hong, S. Park, and H. Kang
251
Bipolar Resistive Switching Memory Characteristics Using Al/Cu/GeOx/W Memristor S. Maikap and S. Rahaman
257
Author Index
263
viii
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