Wavy Channel Architecture Thin Film Transistor (TFT) Using Amorphous Zinc Oxide For High-Performance And Low-Power Semiconductor Circuits Amir N. Hanna, Aftab M. Hussain, and Muhammad M. Hussain
Integrated Nanotechnology Lab, Computer Electrical Mathematical Science and Engineering Division, King Abdullah University of Science and Technology, ThuwaI 23955-6900, Saudi Arabia, E-mail:
[email protected] Abstract
We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling. Introduction
Amorphous metal oxide semiconductors have recently shown potential for flexible, large-area electronics [1]. However, in order to fabricate circuits operating above 100 MHz, the TFT transit frequency, fT, which quantifies the speed of the devices, must be improved [2]. For a given channel material, besides Vr engineering, gate length (Lg) scaling is the major approach for improving fT. There are two main approaches for Lg scaling: (i) top down lithographic scaling, which has been shown for amorphous In-Ga-Zn-O (IGZO) TFT down to Lg of 180 nm [3]; this approach, however, is both expensive, as well as, suffers from sensitivity of TFT properties such as saturation mobility to process conditions, such as gate-to-contact spacing, and the shape of the active area. (ii) Non-lithographically defined gate length using vertical channel TFT architecture [4]. Although, it is less expensive compared to the first approach, the TFT properties suffer immensely from both gate leakage and gate-to source/drain overlap capacitance. The new approach - we are reporting improves Om per unit device width by increasing the device width vertically without chip area penalty, as well as, improves the field effect mobility, liFE, due to high electric field at fin corners, which enhances the field effect mobility, as reported in our previous work [5-7]. Experimental section
Fabrication process details are shown schematically in Fig. 1. We start by first patterning n-type silicon wafer into 4 /lm wide fins, which are 2 /lm deep with a pitch of 4 /lm, thus allowing increasing device width by 50%. This is followed by depositing 50 nm of atomic layer deposition (ALD) aluminum oxide (AI203) for device isolation from the substrate. Then, we deposit aluminum (AI) gate by sputtering and lift-off. A 25 nm thick AI203 is then deposited by ALD as a gate dielectric. Then titanium-gold (Ti-Au) source/drain are deposited by sputtering and lift-off. Finally, ZnO channel is deposited by ALD, and devices are isolated by a combination of wet etched in dilute HF, and RIE for exposing the bottom AI gate. Device Characteristics
We have fabricated devices of 5 different gate lengths, namely 50, 30, 20, and 10 /lm gate lengths. Fig. 2(a) shows an optical micrograph of 10 /lm WC TFT. Fig. 2(b) shows a side view of the WC device showing 4 /lm wide fins, with 8 /lm pitch, and 2 /lm height, which we refer to as 4 /lm 1-1 device. Figs. 3(a, b) show the transfer and output characteristics of the 50 /lm device, the WC and planar devices have threshold voltage 4.6 and 3.9V, respectively. Output characteristics show that the WC TFT consistently had 2x the output current of the planar TFT consuming the same chip area. Similar trend was shown for gate lengths down to 10 /lm (Figs. 4(a, b», where the WCTFT shows an output current of 1.8 mA while the planar counterpart shows 0.9 mA drive current. When analyzing the saturation mobility of both devices (Fig. 4(c», we found that the WC TFT has 50% higher mobility compared to the planar TFT, taking into account the extra device width in the /lsat calculation. Conclusion
We have shown a Wavy Channel architecture for amorphous oxide TFT showing better DC, characteristics compared to the conventional planar TFTs due to both the extra device width, as well as, enhanced liFE, showing a viable alternative to aggressive Lg scaling for high performance, low temperature, oxide based circuits References [1] E. Fortunato et al., Adv. Mater. vol. 24, pp. 2945, (2012); [2] S. Sze and K. Ng, Physics of Semiconductor Devices, 3rd ed. Wiley
Interscience, 2007, pp. 303; [3] S. Jeon, et al., Appl. Phys. Lett. vol. 99, pp. 082104, (2011); [4] L. Petti, et al., IEDM Tech. Dig., pp. 296,
(2013); [5] A. Hanna, et al., Appl. Phys. Lett. vol. 103, pp. 224101, (2013); [6] A. Hanna, et al., IEEE Trans. Elect. Dev. vol. 61, pp. 3223,
(2014); [7] A. Hanna, et al., physica status solidi
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