Envisaged network architecture and implementation of ... Network implementation ofdemonstrator ... prototype wireless activity monitor is being developed to.
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Wireless Activity Monitor Using 3D Integration Ric van Doremalen, Piet van Engen, Wouter Jochems, Ad Rommers, Geert Maas Philips Applied Technologies, Eindhoven, The Netherlands Shi Cheng, Anders Rydberg, University ofUppsala, Sweden Thomas Fritzsch, Jiirgen Wolf, FhGIIZM, Berlin, Germany Walter De Raedt, Roelof Jansen, Philippe Miiller, IMEC, Leuven, Belgium Eduardo Alarcon, Mihai Sanduleanu, Philips Research, Eindhoven, The Netherlands (M. Sanduleanu is now with IBM, Watson Laboratories, Yorktown Heights, USA) Abstract-Unobtrusive and continuous measurement of body parameters such as activity, movement, heartbeat, temperature and oxygen level in blood offers many opportunities in the health and fitness area: distant patient monitoring, rehabilitation support, activity stimulation, improved training programs in sports and even sleep management become possible. Enablers are small wireless body sensors sending the data to a computer or communication device. In the European project e-CUBES, a prototype wireless activity monitor is being developed to demonstrate this can be realized by stacking integrated passives, embedded thinned IC's and SMDs. In the device functional layers are stacked and realized in different technologies: silicon substrate with integrated passives, embedded thinned active dies (transmitter and processor), redistribution layer and SMDs on a PCB which is again stacked on the silicon. The antenna is realized on the silicon backside. The accelerometer is mounted as SMD on the silicon. To enable low power data transfer and a small antenna, a 17GHz transmitter and resonator have been developed and are integrated in the demonstrator. The integrated design and design considerations as well as the testing of the wireless sensor and its functional parts are explained.
Wireless sensor nodes are central elements in important, new application areas as diverse as, for instance, body area networks with bio-sensing, monitoring of concrete building structures, home automation, and distributed monitoring in airplanes. Markets relating to body area sensor networks are e.g. outpatient care (patients being monitored at home) and sports training. Two product-features of general importance in these markets are: comfort and ease of use. Realizing these features is much advanced by miniaturization. Currently, miniaturization is normally done by integration in IC's, or by vertical stacking of IC's connected by wire bonding. In this presentation, we will explore another way of 3D stacking entailing vertical connections that are integrated on the Si-Ievel. This opens up new possibilities, such as e.g. tight integration of mixed technology and very low
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interconnect parasltlcs. Exploration of this technology is made concrete in the development of a demonstrator node, which is undertaken within the European project e-CUBES. To complete the demonstrator, SMDs and a small PCB are soldered on the 3D stack. The partners that are involved in the demonstrator are' Philips Applied Technologies, Eindhoven IMEC, Leuven, Belgium FhG/IZM, Berlin, Gennany
University ofUppsala, Sweden Philips Research, Eindhoven, The Netherlands
System architecture, Application, assembly and packaging 3D Si-Ievel integration technology, 3D-Si layout 3D Si-Ievel integration technology, flip chip, SMD assembly on 3D-stack RF feeding structure and antenna Transmitter and oscillator design and realisation
The envisaged network is basically a star network, consisting of a number of wearable sensor nodes communicating with a central node. The latter can be e.g. a mobile phone. The practical implementation of the demonstrator will be simpler: one-way communication from the sensor nodes to a central, PC-based node. Both the envisaged and implemented network architectures are shown in Fig. I
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Wearable sensor nodes Wireless body network communication
Wearable central unit
(e.g. a mobile phone) Long distance
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Network implementation of demonstrator
Fig. 1. Envisaged network architecture and implementation of
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Fig. 2. Sensor node electronic architectnre
The sensor node electronic architecture consists of a number of functional blocks: • Sensor block consisting of a 3D accelerometer with ADC. This type of sensor is a necessary component in many on-body applications. • Processor block; essentially a flP which processes the sensor data, plays a role in power management and controls the transmitter. • Transmitter block. The main components are a novel, one-chip 17.2 GHz transmitter, expounded in the section 2.2, and a one-chip 8.6 GHz resonator. • Antenna with slot-coupled feeding structure, see section 2.4 below. • Power management block with, among other things, a re-chargeable battery. The power management block is made on a small PCB. All other above-mentioned modules are incorporated in the 3D Si stack. C.
The 17 GHz frequency was chosen for a number of reasons: • It allows a small antenna (a few mm2 ). • It allows a very small distance, of the order of 1 mm, between the antenna and its underlying ground-plane; with the commonly used frequency 2.4 GHz, this distance is 7 x as large. • This frequency is allowed in Europe. • A one-chip transmitter for this frequency (design Philips Research) is basically suited for very low power, 1 nJlbit (not yet realized in the proto chip that we use in the demonstrator). Future developments of the chip target integration of the transmitter, oscillator and a receiver within the same area « 1 mm2 ), reduced power dissipation, and frequency increase to 24 GHz (allowed in both Europe and USA).
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3D acceleration sensor
Kionix, the supplier of the 3D MEMS-based accelerometer (KXPS5) describes the principle as follows on their website: "The sensor element functions on the principle of differential capacitance. Acceleration causes displacement of a silicon structure resulting in a change in capacitance. An ASIC, using a standard CMOS manufacturing process, detects and transforms changes in capacitance into an analog output voltage, which is proportional to acceleration. This voltage is digitized by an on-board AID converter and is accessed via an interintegrated circuit (I2C) bus or serial peripheral interface (SPI)." As the accelerometer is a standard packaged device, no special measures have been taken. E.
Physical architecture and packaging Antenna
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Coil: Wireless charging Wireless wake-up
Fig. 3. Physical architectnre of sensor node, drawing not on scale
The physical architecture is given in Fig. 3, showing a number of layers stacked on top of one another. From bottom to top these layers contain: 1. PCB with power management electronics. The area is 10.1 x 18.7 mm2 2. 3D Si-stack. Area is 8.0 x 18.0 mm2 3. PCB layer with low RF absorption 4. Antenna structure: patterned Cu layer on abovementioned PCB. The Si-stack, ill 2, consists of a number oflayers in itself: 2a Substrate, 0.7 mm thick. 2b Layer with integrated passives and the slot structure (red line). 2c Layer, thickness a few times 10 flm, with two embedded actives, the radio (0.9 x 0.95 mm2 ) and the flP (5.2 x 5.2 mm2 ), as well as vertical interconnects. 2d Redistribution layer. 2e SMD' s. In this layer are also the solder balls for connection to the PCB.
DI!~1-3April, • Fig. 4. Layout of the 3D Si stack within the H&F demonstrator
The linearly-polarized antenna is fed by a 50 Q microstrip line, using aperture-coupling through a H-shaped slot in the ground plane of the 3D Si stack. Fig. 4 shows the layout of one of the designs. Note the white "H", which is the slotcoupling structure for the antenna. Two dies have been embedded: The processor (Dl) and the transmitter (Nl). Close to the transmitter (Nl), the 200llm thick oscillator flip chip is mounted. Embedding was considered too risky. The assembly of the large X-tal component (Y2) on top of the embedded Il-processor (Dl), reduces the required area of the 3D Si stack. However, the other large and heavy component, the MEMS accelerometer (N2), has been placed next to the embedded processor to limit the processing and yield risk. The other SMD components have size 0201. Fig. 5 shows the device with its encapsulation. The 3D Si stack is soldered on the power management PCB with solder balls. A hole is left out in the cover above the antenna structure so as not to interfere with the emitted radiation. Hermetic sealing can be obtained by application of a filler material around the circumference of the hole. The outer dimensions of the encapsulation are 20.0 x 11.4 x
which simplifies antenna modeling. As is seen in Fig. 6, a rectangular patch etched on a 508 urn thick Rogers 5880 substrate (c:r=2.2, tan8=0.009) is mounted on top of the Sistack. This linearly-polarized antenna is fed by a 50 Q microstrip line (metal 3 in Fig. 6), using aperture-coupling through an H-shaped slot in the ground plane. The Rogers substrate thickness has been designed for optimum impedance bandwidth and antenna gain. Antenna impedance matching and resonance frequency can be retuned after testing by adjusting only the patch width (Wpatch) and length (Lpatch) on the Rogers substrate. It is a cost effective approach because re-design of the Si-stack is not needed.
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Antenna and feeding structure
A miniaturized wireless sensor node necessitates a fully integrated antenna. An antenna is strongly affected by the surroundings, and the situation is even more complicated due to the complex physical structure. Therefore, a simplified model has been used for the electro-magnetic simulation and the design of antenna and feeder.
Fig. 6. Schematic of the linearly-polarized patch antenna integrated in the sensor node. Some dimensions: L~18 mm, W~8 mm, S~760 urn.
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Fig. 5. Mechanical design drawing, without and with encapsulation
Fig. 6 depicts the outline of the simplified model of the antenna integrated in the sensor node. A ground plane (metal 1 in Fig. 6) acting as a shielding layer is applied onto the Si substrate. The ground plane significantly reduces the influence of other electronics on antenna performance,
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Fig. 7. Simulated reflection coefficient of the linearly polarized patch antenna.
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April, Rome, ltaly PROCESSES
In the next sections the processes to make the demonstrator are described. As no full functional 3D-stack has been completed yet at the writing of this document, short loops have been done using a dummy 3D Si-stack. A.
Fig. 8. Simulated 3D radiation pattern. The results of full-wave simulations of the assembly are presented in Fig. 7, reflection coefficient of the antenna and Fig. 8, 3D radiation pattern. Impedance bandwidth at 17.2 GHz is 10%. The calculated antenna gain is 5.4 dBi, radiation efficiency 97%, and front-to-back ratio 13.4 dB. The good radiation characteristics are due to the use of low loss substrate material and high resistivity silicon. This antenna mainly radiates upwards which is appropriate for off-body communication. G. Design considerations
Some design considerations are summarized in TABLE 1 TABLE 1 DESIGN CONSIDERATIONS
Issue Absorption of antenna signal Signal to antenna Integrated passives cannot be replaced afterwards HF frequency matching Energy storage in small volume Waterproof Limited availability of wafers, needed for embedding Testing dies may damage the dies HF Connection between transmitter and oscillator
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Design implication Antenna on outside, hole in package Antenna on backside of Si stack. By slot coupling no connections are needed. Critical values as SMD so replacement is possible Linear polarization Antenna can be replaced by other size Small rechargeable coin battery (010 mm) Wireless charging and wake-up using coil Only processor and transmitter integrated. Other devices as SMD Special test designs and test strategy (sampling) Oscillator die as bare die flip-chip to keep leads short
The realization of the 3D silicon demonstrator is based on an advanced multilayer technology (IPD - integrated passives device technology). In addition to the well established BCB-copper multi layer technology on wafer level, integrated passive structures and ultra thin chips are embedded into the layer stack. Different versions of the 3D demonstrator were realized at IMEC and Fraunhofer IZM. After the wafer thinning and singulation process, the separate thinned dice are aligned on the integration substrate (already containing resistors and capacitors) and the specially designed bond tool is removed (Fraunhofer IZM process) or the carrier is removed through immersion in a solvent for the glue layer (IMEC process). Next, the die embedding process starts with the fabrication of HARVls (High Aspect Ratio Vias). HARVls are used to connect the dies to the underlying passives layers. The HARVI process only requires one additional mask layer as compared to the standard IPD flow. High aspect ratio connections can be achieved. The process starts with the deposition of electroplated high aspect ratio copper studs (HARVI) which fonn the connection between first (bottom) and second metal layer. The following dielectric polymer layer has to level the topography of the attached chip and the electroplated studs. The [mal cross-section is shown in Fig. 9 and a picture of an embedded test die is depicted in Fig. 10. Integration Passives Thinned die Die attach Active circuit HARVI BCB dielectric Cu Fig. 9. Schematic cross-section of embedded die with Harvi, Cu interconnect and BCB dielectric layers
disturb the high frequency signal. Therefore the challenge is to get a good and reliable connection between the large 3D Si stack and the PCB despite the stress built-up during cool down after soldering. Therefore, thermo mechanical FEM simulations are being done on the integrated assembly. For evaluating the design and assembly process, daisy chains and special antenna test devices have been made.
Fig. 10. Picture of thin die embedded and connected to the passives substrate
After finishing the last wafer level process step, solder paste is printed on a singulated 3D Si stack and the SMD components are placed. The oscillator chip (thinned down to 200 11m and a with a continuous sputtered Al layer on the backside) is assembled in flip chip technology on the 3D Si substrate after the reflow of SMD components. Electroplated SnAg solder bumps on the oscillator chip are used for the interconnection between chip and 3D stack substrate. Altogether 36 peripherically arranged bumps with diameter of 751lm in a pitch of 125 11m are placed on every oscillator chip. After deposition of flux material the chip is attached without any additional solderpaste on the substrate by a high accuracy flip chip bonder tool. Afterwards the chip is fixed by a second reflow step on the substrate. Then SnBi solder paste is dispensed and Alpha Solder spheres (SnlO/Pb90, 0 30 mil) are placed manually on the 3D Si stack with SMDs. The reflow temperature of 160°C ensures that only the SnBi melts and the SnPb spheres do not deform. This ensures the required stand-off. B.
Fig. 12. 3D Si stack soldered on PCB with solder balls, design and specimen (on dummy Au-plated Si)
As conventional soldering on a battery would cause unacceptable temperature raise of the battery, Ni leads (strips) are laser welded onto the battery. The leads defme a stand-off of 1.7 mm from the PCB, which is needed because there will be SMDs between the battery and the PCB. After the welding process, the charging/discharging cycles of the battery have been tested and the effects of welding were not found to be significant. The battery with leads is laser welded onto the Au-plated Nickel pads on the PCB. The miniature coil is specially designed for wireless charging of the e-CUBE. Just as the battery, also the ferrite needs to be placed over the SMDs. Therefore it is glued on studs (1 mm2), see Fig. 13. (Special handling tools are used to ensure that the ferrite is well positioned on and parallel to the bottom of the housing, to ensure efficient wireless charging).
PCB with power management electronics
The PCB is made of FR4 (Isola DEl04 IMP). The dimensions are 10.1 x 18.7 mm2. As the CTE is slightly anisotropic, the lowest CTE is designed in the length direction. The SMDs for power management and Au plated nickel welding pads are soldered with standard SAC in a reflow oven (at 235°C). The result is shown in Fig. 11.
Fig. 13. Ferrite and charging coil (assembly), design and specimen
Fig. 11. The PCB of the H&F demonstrator
The antenna PCB is placed with an aligned assembly tool (Datacon) to assure 20 11m alignment accuracy to the antenna coupling structure in the 3D Si stack and glued on the backside of the silicon (Fig. 14). The choice of glue used depends on the intended use of the stack. In the beginning, removable glue is used for testing, so different antenna shapes can be tested.
To connect the 3D Si stack with solder spheres onto the PCB, SnBi solder paste is dispensed on the PCB, the 3D Si stack is placed on the PCB and the assembly is heated in a reflow oven at 160°C. The result is shown in Fig. 12. No underfiller is allowed in the area of the transmitter, oscillator and slot coupling structure, because it would
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Fig. 14. Antenna, design and specimen
The housing protects the sensor node (mechanical stability, moisture). The bottom below the charging coils is only 0.3 mm thick in order to ensure good wireless charging performance. The antenna is placed in a hole in the cover so the housing should not disturb the antenna performance. For the demonstrator, the housing consists of Accura 60SL, a material suitable for a rapid manufacturing process. The module is placed in the box shown in Fig. 15. Ifnecessary, small glue dots will be used for fixation. To make the sensor node water proof, the lid will be sealed to the box and to the silicon.
CONCLUSIONS AND OUTLOOK
The results that have been obtained so far indicate that 3D integration on the Si level will be feasible and gives advantages over existing technology. The demonstrator device will be used for further application studies and it will serve as a basis for subsequent work. This will entail both an extension towards more embedded components in a larger number of vertically stacked layers, achieving reduced overall thickness, as well as the development of an industrial technology basis.
The support from the European Commission in the Research Project e-CUBES, contract number 1ST-026461, is gratefully acknowledged. Furthermore, the co-operation and fruitful discussions with all the e-CUBES partners have been very valuable. Also the contribution of Texas Instruments, who supplied the necessary MSP430 microProcessor wafers, has been essential for the development of the demonstrator.
Fig. 15. Housing, design and specimen
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