to form wireless interconnects in foundry digital CMOS tech- nologies has been demonstrated. The key challenges includ- ing the effects of metal structures ...
Wireless Communications Using Integrated Antennas' K. K. 0, K. Kim, B. Floyd, J. M e h t a , H. Yoon, C.-M. Hung, D. Bravo, T. D i c k s o n , X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. C h e n , E Martin*, and J. Brewer Silicon Microwave Integrated Circuits and System Research Group (SiMICS) Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, 3261 1 *Motorola Labs, 8000 West Sunrise Blvd., Plantation, FL, 33322 Abstract The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, lieat removal, packaging, and interaction between transmitted and received signals and nearby circuits appear to be manageable. This technology can potentially be applied for iniplementation of a true single chip radio, on-chip and inter-chip communication systems, WID tags, and others. Introduction Scaling of MOS transistor length to 0.10 pm and below has made the implementation of CMOS circuits operating at 20 GHz and higher feasible [11-[3]. At 24 GHz, the wavelength of electro-magnetic waves in free space is 12.5 mm and in silicon it is 3.7 mm. This means a quarter wave antenna needs to be only 3 and 0.9 mm in free space and silicon. These in conjunction with the increases of chip sizes to - 2 cm x 2 cm have made the integration of antennas for wireless communication possible. Integrated antennas could potentially be used to relieve the bottleneck associated with global signal distribution inside integrated circuits such as for lowering clock skew 141 (Fig. I). Integrated antennas could also be used for data communication between integrated circuits to lower the WO pin counts, thus reducing the form factor and packaging costs. When integrated with sensors and a power source, a transceiver with integrated antennas could provide a communication link for sensor network nodes (bnode) (Fig. 2). The nodes can he the size of a grain of rice (-3" x -3 mm x -1") and sufficiently inexpensive that they may he disposable. Such nodes could help to accelerate the realization of the Smart Dust vision 151. This paper reviews the status of key technologies required to implement these interconnect systems as well as challenges and potential solutions. This paper discusses the paths for signal propagation [6], performance of integrated antennas on 10-20 Q-cm silicon substrates commonly used for CMOS and BiCMOS technologies [71-[9] circuits which could be implemented in mainstream CMOS technologies for this type of applications [10],[11] and demonstrations of wireless interconnects [10]-[12]. The key challenges including the effects of metal structures associated with integrated circuits [13]-[15], heat removal [12], packaging, and interac#This work is supported by SRC (Task ID: 85.5). except the pnade elfort which is supported by DARPA (N66001-03-1-8901).
tion between transmitted and received signals and nearby circuits [16]-[19] are discussed. ar&'MCM) lntegialed clrc"lts
transmined clock Signal
Transmining Antenna (With parabolic reflector)
-
'
Fig.1: Wireless Clock Receiver Block Diagram
Figure 3 shows some ofthe possible paths for signal propagation within an integrated circuit. There are a direct path, a path formed by refraction through the SiOl layer and reflection at the interface between the silicodunderlying dielectric layer (AIN), and a path refracted through the SiOz and silicon layers and reflected by the metal chuck, which acts like a heatsink in the back of a die. These paths constructively and destructively interfere. Fig. 4 shows G, versus frequency plots for varying thicknesses of AIN layer between the silicon and metal chuck. The measurements were made using a pair of 2-mm zigzag dipole antennas shown in Fig. 5 and the separation between the antennas was 5 mm. The power transmission gain G, is defined as =
2 IS211 ( 1 -Is1112)(~-Is2212)
Dips due'to destructive interference effects are observed in the plots. As the AIN thickness is increased, the frequencies at which the dips occur are lowered. This is a clear demonstration of the fact that signal transmission and reception are via wave propagation. The addition of a 0.76-mm thick AIN layer improves the power transmission gain by around -10 dB compared to the case when the wafer is in direct contact
111
with the metal chuck. The AIN layer has a thermal conductivity comparable to AI and provides an excellent thermal path for heat removal. Fig. 6 shows the radiation patterns of dipole and loop antennas at 10 GHz, which are consistent with basic antenna theorv. Fig 2 , A conceptual diagram of a b-node.
balls
I6""a
A01
Fig. 3, Some of the possible propagation paths.
fully picked up by the receiver and amplified to generate a digital output signal [121 (Fig. 8). The receiver and transmitting antenna were fabricated using a 0.18-Km CMOS process [Ill. Fig. 9 shows micro-photo graphs of the transmitter and receiver.The area including the antenna is 5.86 x lo5 pm2. The area excluding bond pads is 3.75 x IO5 or (600 x.600) bm2. The receiver consumes 40 mW of power. For the clock application, transmission over 2.2 cm is sufficient for the largest chip projected by the Intemational Road Map for Semiconductors (ITRS) [21]. The power consumption of a wireless clock distribution system using 16 receivers over the areas projected by the ITRS has been estimated and found to be comparable to that of conventional systems [221. This is due to the fact that most of the power consumption of a clock distribution network is expended for driving local loads.
7
Fig. 4, G,vs.
frequency when the AIN propayling layer t ickness IS varied.
10.0
12.0
14.0
16.0
18.0
Frequency(GH2)
As mentioned. clock distribution can he a votential anvlica.. tion for wireless interconnects. In the wireless approach, the clock is transmitted using a monotone cosine wave and the received signal is amplified, divided and buffered to locally provide clock signals. At the 0.18-pm generation, the latency for the wireless clock distribution system will be around 400 pS compared to 1 nS of conventional clock distribution networks. The latencies to all points in a chip must be matched to a tighter tolerance with each generation of technologies to facilitate the increase in clock frequency. The latencies in wireless systems are dominated by the delay through clock receiver circuits and this delay scales down with technology as shown in Fig. 7, while the latency for the conventional system is expected to remain essentially constant. This means for conventional clock distribution systems, the latencies must he matched to a smaller percent of the total latency compared to a wireless clock distribution network. This is a fundamental distinction and may lead to smaller skew for a wireless clock distribution system. In addition, since a single tone cosine wave is used for clock transmission, the dispersion effect which has been suggested to ultimately limit the chip size and clock [ZO] is eliminated. On wafer, a 15-GHz transmitted signal 2.2 cm away from a clock receiver with an integrated antenna has been success-
-
112
-
no
270
Loop Antenna
DlpOle Antenna
Fig 6, radiation patterns of dipole and loop antennas Using an external gaussian lens horn antenna (similar to the system in Fig. l(b)), a clock signal with total skew less than -14 pS can he provided over an area of 3.8 cm x 3.1 cm [23]. This should be sufficient for a system operating -3 GHz and this area is -4X larger than an area which is typically.thought possible for synchronization at such a frequency. Furthermore, receiving antennas can be significantly shorter than I 2000 COnYenIiDnal ClDC Skew Tolerance
1500
P
E 200
0.0
0.0 1997
1999
2001
2003
Yea,
2005
2007
w
Fig. 7, Latencies versus time for clock distrihi on systems. Metal stmctures near antennas can changf nput imped-
ances and phase of received signals. To deal with this, design guide lines to exclude interference structures which significantly change the input impedance and techniques to correct the phase changes are being developed [15]. Another concern is the interference effects between transmitted signal and nearby circuits, and between the transmitted! received signal and switching noise of nearby circuits [16][191. A 1.96-GHz output signal of a 7.4 GHz wireless interconnect is used to drive 100-stage long inverter chains (Fig. IO). This was the first use of a wireless interconnect to drive a digital circuit. As the number of inverter chains is increased, jitter of the received signal increases and ultimately, the receiver fails. This problem has been attributed to changes in the receiver amplifier gain and self-oscillation frequencies of the frequency divider due to the substrate noise injected from the switching inverters. The operation was restored by increasing the transmitted power to compensate for the gain reduction and by re-centering the selfoscillation frequency of the divider [19]. It should he possible to reduce the sensitivity to this problem by using guard rings and a triple n-well process which is starting to be widely available to isolate body nodes of NMOS transistors.
~
0.4
fin=16GHz
6
2 0
-
.-
0.0
0.15
161 K. K i m , W. Bomtad, and K. K . 0 , 2 0 0 1 IEEE AP-S lntl. Symp. and USNUURSI Nat. Radio Sci. Meeting. vol. 2 , pp. 166-169, Boston, MA, July, 2001. 171 K. K i m a n d K. K. 0,Proceedings of Ihe IITC, pp 21-23. San Francisco, CA, Junc 1998. 181 K. Kim. H.Yoon. and K. K. 0, Technical Digest of IEDM, pp. 485.488. San Francisco, 2000. [ 9 ] A. B. M. H., S. Watanabe, T. Kikkawa. IEEE Elec. De". Letts, YO. 23, no. 12,pp. pp. 731-733, Dec. 2002. [IO] B. A. Floyd, K. Kim. K . K . 0. IEEE ISSCC, pp. 328-329, San FranCISCO. CA, Feb. 2000. [ I I ] B.-A. Floyd. C.-M. Hung. and K. K. 0 . IEEE 1. of Solid-State Circuits, vol. 37, no. 5. pp. 543-552, May 2002. [I21 X. Guo, 1. Casena, K. Li. B. Floyd, and K. K. 0 . 2002 Symposium on VLSl Technology, pp. 3 6 ~ 3 7June. , 2W2, HOIIOIUIU. HI. 1131 H. Yoan, K . Kim, and k. K . 0 , 2000 IEEE AP-S Intl. Symp. and USNCIURSI NaI. Radio Sci. Meeting.. pp. 782- 785. Salt Lake City, UT. July 2000. 1141 A. E . M. Harun-ur Rashid. S. Watanabe, T. Kikkawa, X. Guo, and K . K. 0 , 2 0 0 2 IITC. pp. 173-175, San Francisco, CA, 2002. [I51 X. Guo, R . Li and K . K . 0, Accepted to 2003 IEEE AP-S lnll. Symp. and USNUURSI National Radio Science Meeting, 1161 1. Mehla, and K. K. 0 , IEEE Trans. on Electro-Magnetic Compatibilicy. YOI. 44," 0 . 5 . pp. 282~290,M ~ 2002. Y 1171 D. Bravo, H. Yoon, K. Kim, B. Floyd. and K . K. 0 , 2 0 0 0 IITC. pp. 9 I I,San Francisco, CA, June 2000. [I81 T. 0. Dickson. D. Bravo, and K. K . 0 , 2002 IEEE Inremational Symposium on EMC, v d l , pp. 340-344, Minneapolis. MN. Aug. 2002. 1191 T. 0. Dickson, B. Floyd, and K. K . 0. 2002 lntemational lnlerconnect Technology Conference, pp. 154-156. San Francisco, CA, June 2002. [20] A. Deutsch, el al., lEDM Tech. Disesr, Dec. 1998, pp.295-298. Washington D.C.. Dec. 1998. [Z I] The Inremnrionol T r c h m l o ~Roudmpfor y Semiconducrm. SIA. San Jose. CA, 20W. [22] B. A . Floyd, and K . K. 0, Proceedings of the 1999 IITC. pp. 248.251, San Francisco, CA, June 1999. [23]1 W. B o m t a d and K. K. 0. 2002 IEEE AP-S lnll. Symp. and USNCi URSl National Radio Sci. Meeting.. Vol. 3, pp 726.729, San Antonio, TX. [24] R . Li, W. Bomtad, 1. Casena, X. Guo and K . K . 0,Accepred to 2003 lntemational lntercomect Conference. ~
v)
c
i
B -0.05
c
5
niques, vol. 50,issue 9 , pp. 2193-2196. Sep. 2002. 121 C.-M. Hung,L. Shi, 1. Lagnado. and K . K. 0. 2000 VISI Symposium on Circuits, pp. 100 - 101, Honolulu, HI, June 2000. 131 M. Wetiel. L. Shi, K. Jenkins, P. R. de la Housiaye, Y. T a r , P. Asbeck, and I. Lagnado, IEEE Microwave and Guidc Wave Letts. vol. 10, no. IO. pp. 421.423. Oct2000. 141 K. 0 , K . Kim. B. A. Floyd. 1. Mehla, 2nd H. Yapn. 1999 Gout. Microcircnil Appr. Conf. Dig. Papers, pp. 306-309. Monterey CA, Mar. 1999. 151 B. Wameke. M. Last. B. Liebowitr. K . S. J. Pisrcr. Computer. vol. 34. no. 1,pp. 44-51,Jan2001.
-0.4 '
Times(ns)
Times(ns)
LOns
Fig. 8, Transmitted and the digital output signal of a clock receiver 2.2 cm away from the transmitting antenna. Transmitter
Fig. 9, A transmitter and receiver pair fabricated in a 0.18-um
Conclusions
Fig. 10, A7.4GHz clock receive surrounded by inverter chain driven by the receiver.
The speed improvement and increase of die size in silicon integrated circuits technology have made integration of antennas feasible. This technology can potentially be used to increase clock frequency of digital systems, and to reduce the number of U 0 pins, size, and weight of electronic systems. References Ill B.-A. Floyd and K. K . 0. IEEE Trans. on Microwave Theory and Tech'
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