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XsSOI, CESL, TiN Gate - IEEE Xplore
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XsSOI, CESL, TiN Gate - IEEE Xplore
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CEA LETI-MINATEC, 17 rue des Martyrs, 38054 Grenoble, France ; °
IMEP
, MINATEC, BP 257, 38016 Grenoble, France. * STMicroelectronics, 850 rue J.
4A-5
×≈
50
978-4-900784-03-1
σ
2007 Symposium on VLSI Technology Digest of Technical Papers
150
300
+100%
100
0,Ref
/µ
t-CESL
-600 -400 -200 ON
0
200 400 600 800
(µA/µm)
Stressor
Stress
n
p
n
p
c-CESL
Comp. X
-30
+60 -100
t-CESL
Tens. X
+30
-60 +100 +12.5
TiN (or c-CESL) Comp. Y + narrow fins
-20
-50
+49
+28
+49 +28
+49
+28
Comp. Z
-12.5
2D stress optimization for both n & pMOS : SINGLE t-CESL + TiN + Narrow fins
t-CESL c-CESL
-50 holes
100
XsSOI
50
c-CESL
0
t-CESL
3 2.5
lines= ; dashed= V =50mV ; L =10µm D G open=sSOI ; full=XsSOI black=nMOS ; red=pMOS XsSOI n
XsSOI n
50
sSOI n XsSOI p sSOI n
XsSOI p sSOI p
0
sSOI p
sSOI
100
0
1000
Gate Length (nm)
Top view normalisation ; V =50mV ; L =10µm D G lines= ; dashed= Ref. c-CESL t-CESL
2
600
1.5
50
100
150
200
Fin Width (nm)
250
BOX overetch=
-750MPa
0nm
0
Z
2nm
X
Y
550MPa
10nm
400
nMOS
σ
σYY
YY
200
1
σ
pMOS
ZZ
σZZ
0 Mean 3nm under gate stack
0.5 0
100
50
100
150
200
250
0
100
200
25nm
Fin Width (nm) Fin Width (nm) 2.5
300
(2T +W) normalisation ; V =50mV ; L =10µm Si
D
lines=simu (Fig. 9) + model piezo symb=exp
2
e ff
1 0.5
+55%
0 0
150
pMOS
100 50
50
100
nMOS pMOS
200
+18%
L
G
150
Fin Width (nm)
200
0
250
c-CESL
XsSOI
700
t-CESL
-10
600
Ref.
XsSOI
I
XsSOI sSOI
Re f.
(A/µm)
SOI (open) SOI (closed)
I
OFF
-8
Transconductance (µS/µm)
Top view normalisation
-11
electrons
-50 W=10µm 10
500
W=50*50nm Leff
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