www.ietdl.org Published in IET Power Electronics Received on 20th February 2013 Revised on 7th August 2013 Accepted on 10th August 2013 doi: 10.1049/iet-pel.2013.0128

ISSN 1755-4535

Zero voltage switching DC converter for high-input voltage and high-load current applications Bor-Ren Lin, Chih-Chieh Chen Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou City, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: A new DC/DC pulse-width modulation (PWM) converter with the functions of zero voltage switching (ZVS) for power switches and zero current switching (ZCS) for rectiﬁer diodes is presented for high-input voltage and high-load current applications. Three-level PWM circuit with two clamped diodes and one ﬂying capacitor is adopted to achieve ZVS turn-on for all power switches, to balance two input capacitor voltages and to limit the voltage rating of each switch at one-half of input voltage. Two three-level PWM circuits with the same power switches are used to share the load current for medium power applications. Series–parallel resonant converter or LLC (Lr, Lm and Cr) converter is adopted to achieve ZCS turn-off for rectiﬁer diodes. Thus, the switching losses of power switches are reduced and the reverse recovery losses of rectiﬁer diodes are eliminated. In order to high load current application, four centre-tapped rectiﬁers are connected in parallel to reduce the current rating of rectiﬁer diodes and transformer windings. Experiments are provided to verify the effectiveness of the proposed converter.

1

Introduction

For three-phase systems such as 380 Vrms or 480 Vrms, a diode rectiﬁer with power factor correction (PFC) is generally used in the front stage to reduce the line current harmonics in order to meet the international standard IEC 61000-3-2 or IEEE 519 and to provide a high DC bus voltage. Generally, the DC bus voltage of the three-phase AC/DC converter with/without PFC is in the range of 530–800 V. Thus, the voltage rating of power switches in the second stage DC/DC converter such as phase-shift full bridge converter should be greater than 800 V. In order to use low voltage rating metal oxide semiconductor ﬁeld effect transistors (MOSFETs) (600 V) with high switching frequency instead of high-voltage rating IGBT (1200 V) in the second stage DC converter with high frequency and high-power density demand, three-level or multilevel converters [1–4] have been proposed as the DC/DC converters for high input voltage applications. Three-level zero voltage switching (ZVS) converters [5–17] have been proposed to reduce the switching losses at the desired load range. The basic three-level diode clamped DC converter has been discussed in [5–9]. In [10–12], the additional auxiliary circuit is added in the three-level diode clamped converter to extend the ZVS range. In [13– 17], a ﬂying capacitor is added in the primary side to balance two input capacitor voltages and an active circuit is added in the secondary side to achieve zero current switching (ZCS) turn-off of rectiﬁer diodes. However, the ZVS of these topologies are not wide or full load range 124 & The Institution of Engineering and Technology 2013

and rectiﬁer diodes have reverse recovery losses. Two-level LLC converters [18–21] can achieve ZVS turn on for power switches and ZCS turn off for rectiﬁer diodes within a wide range of input voltage and load conditions. However, the voltage stress of active switches in these circuit topologies is equal to input voltage. For high input voltage applications, three-level LLC converter is presented in [22–26]. However, the more power switches are used in [26] and the current stress at the secondary side in these circuit topologies is high for heavy load condition. It is a better way to use parallel connection at the secondary side for high load current application in order to reduce the current rating of rectiﬁer diodes and transformer windings. A new DC/DC converter with ZVS/ZCS is presented for high input voltage and medium power applications. In order to use power semiconductors with low-voltage rating in high input voltage applications, three-level DC converter with two clamped diodes and one ﬂying capacitor is adopted in the proposed circuit. Thus, the voltage at each power switch is clamped at one-half of input voltage and two input capacitor voltages are automatically balanced through a ﬂying capacitor. Two three-level pulse-width modulation (PWM) circuits with the same power switches are used to share the load current for medium power applications. Thus, the switch counts in the proposed converter are less than the conventional parallel three-level converter with eight power switches. The LLC converter is used in the primary side of transformer in order to achieve ZVS turn on for all switches and ZCS IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org turn off for rectiﬁer diodes if the switching frequency is less than the series resonant frequency. The switching loss of MOSFETs and the reverse recovery loss of diodes are eliminated. The PWM control instead of frequency modulation (FM) control is used to regulate output voltage. Four centre-tapped rectiﬁers are connected in parallel to reduce the current rating of rectiﬁer diodes and transformer windings for high load current application. The primary windings are connected in series in order to balance the secondary side currents. Finally, experiments based on a laboratory prototype are provided to verify the operation principle of the proposed converter.

2

Circuit configuration

Fig. 1 shows the circuit conﬁguration of the proposed converter for high input voltage (Vin = 600 V) and high output current applications. There are two three-level ZVS circuits connected in parallel in the proposed converter. The ﬁrst three-level circuit includes Cin1, Cin2, Da, Db, Cf, S1–S4, C1–C4, Cr1, Lr1, T1–T2, D1–D4, Co and Ro. The second three-level circuit includes the components of Cin1, Cin2, Da, Db, Cf, S1–S4, C1–C4, Cr2, Lr2, T3–T4, D5–D8, Co and Ro. Input capacitances Cin1 and Cin2 are equal and large enough to be two input voltage sources vCin1 = vCin2 = Vin/2. S1–S4 are power MOSFETs stressed with Vin/2. C1–C4 are the output capacitances of S1–S4, respectively. Da and Db are the clamped diodes. Cf is a ﬂying capacitor with the average voltage of Vin/2. Cr1 and Cr2 are the series resonant capacitances and the average capacitor voltages VCr1 = VCr2 = Vin /2. Lr1 and Lr2 are the series resonant inductances. Lm1–Lm4 are the magnetising inductances of transformers T1–T4, respectively. D1–D8 are the rectiﬁer diodes. Ro is the load resistance and Co is the output capacitance. Two three-level circuits share the same power switches S1–S4, the clamped diodes Da and Db, and the ﬂying capacitor Cf. In each three-level circuit, two transformers are connected in series at the primary side and connected in parallel at the secondary side to balance the secondary side currents for high output current applications. The PWM signals of S1 and S4 are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of S2 and S3 are complementary each other. Based on the on/off states of S1–S4, three voltage levels Vin, Vin/2 and 0 are generated on the AC terminal voltages vab and vbc. Since the average voltages of Cr1 and Cr2 are all equal to Vin/2, the other three voltage levels Vin/2, 0 and –Vin/2 are generated on the terminal voltages vp1 and vp2. Each centre-tapped rectiﬁer supplies one-fourth of load current such that the current rating of each transformer secondary winding and the rectiﬁer diodes are reduced.

Fig. 1 Circuit conﬁguration of the proposed converter IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

3

Operation principle

Fig. 2 illustrates the key PWM waveforms of the proposed converter. The duty cycle of switches S1–S4 is equal to 0.5. The PWM signals of S2 and S3 are phase-shifted with respective to the PWM signals of S1 and S4, respectively. The phase-shift PWM scheme is adopted to regulate the output voltage against the input voltage and load current variations. The following system analysis is based on the assumptions of (i) VCin1 and VCin2 are two balanced voltage sources, (ii) C1 = C2 = C3 = C4 = Coss, Cr1 = Cr2 = Cr and Cr > Coss, (iii) VCr1 = VCr2 = VCf = Vin /2, (iv) Vo is a constant output voltage, (v) Lm1 = Lm2 = Lm3 = Lm4 = Lm, Lr1 = Lr2 = Lr and Lr ≪ Lm , (vi) the turns ratio of transformers T1–T4 is n = np/ns1 = np/ns2 and (vii) MOSFETs S1–S4 and diodes D1–D8 and Da–Db are ideal. Based on the on/off states of S1–S4, Da–Db and D1–D8, there are ten operating modes in the proposed converter during one switching period. The equivalent circuits of these operating modes are shown in Fig. 3. Prior to t0, S1 is conducting and inductor currents iLr1 . 0 and iLr2 , 0. 3.1

Mode 1 [t0 ≤ t < t1]

At t0, C2 is discharged to zero voltage. Since iLr2 (t0 ) − iLr1 (t0 ) , 0, the anti-parallel diode of S2 is conducting and switch S2 can be turned on at this moment to achieve ZVS. The AC terminal voltages vab = 0 and vbc = Vin. The primary side voltage vp1 = –vCr1 < 0 and vp2 = Vin–vCr2 > 0 such that D2 and D4 in the ﬁrst three-level circuit and D5 and D7 in the second three-level circuit are conducting. The magnetising inductor voltages vLm1 = vLm2 = −nVo and vLm3 = vLm4 = nVo .

Fig. 2 Key waveforms of the proposed converter 125

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Fig. 3 Operation modes of the proposed converter during one switching cycle a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10

The magnetising currents iLm1 and iLm2 decrease and iLm3 and iLm4 increase in this mode. Lr1 and Cr1 in the ﬁrst circuit are resonant with the applied voltage 2nVo. Lr2 and Cr2 in the 126 & The Institution of Engineering and Technology 2013

second circuit are resonant with the applied voltage Vin − 2nVo. Power is transferred from Vin to Ro through S1, S2, T3, T4, Lr2, Cr2, D5, D7 and Co. In ﬁrst circuit, the energy stored in IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org Lr1 and Cr1 is transferred to output load Ro through S1, S2, Cr1, Lr1, T1, T2, D2, D4 and Co. 3.2

Mode 2 [t1 ≤ t < t2]

At t1, S1 is turned off. Since iLr2 (t1 ) . 0and iLr1 (t1 ) , 0, C1 is charged and C4 is discharged linearly. Since C1 and C4 < < Cr1 and Cr2, the inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drainto-source voltage of S1 is limited by C1 and C4 such that S1 is turned off at ZVS. If the energy stored in Lr1 and Lr2 is greater than the energy stored in C1 and C4, then C4 can be discharged to zero voltage. The ZVS condition of S4 is given as Lr (i2Lr1 (t1 ) + i2Lr2 (t1 )) ≥ Coss Vin2 /2 3.3

(1)

Mode 3 [t2 ≤ t < t3]

At t2, C4 is discharged to zero voltage. Since iLr2 (t2 ) . 0 and iLr1 (t2 ) , 0, the anti-parallel diode of S4 is conducting. Therefore S4 can be turned on at this moment to achieve ZVS. The AC terminal voltages vab = vbc = Vin/2. The rectiﬁer diodes D2, D4, D5 and D7 are still conducting in this mode. The magnetising inductor voltages vLm1 = vLm2 = −nVo and vLm3 = vLm4 = nVo such that the magnetising currents iLm1 and iLm2 decrease and iLm3 and iLm4 increase. Lr1 and Cr1 in circuit 1 are resonant with the applied voltage Vin/ 2 + 2nVo and Lr2 and Cr2 in circuit 2 are resonant with the applied voltage Vin/2 − 2nVo. In this mode, the ﬂying capacitor voltage vCf = vCin2 = Vin /2. 3.4

Mode 4 [t3 ≤ t < t4]

At t3, iLm1 = iLm2 = iLr1 and iLm3 = iLm4 = iLr2 such that the rectiﬁer diodes D1–D8 are all in the off-state. Cr1, Lr1, Lm1 and Lm2 in circuit 1 are resonant with the applied voltage Vin/2. In the same manner, Cr2, Lr2, Lm3 and Lm4 in circuit 2 are resonant with the applied voltage Vin/2. 3.5

Mode 5 [t4 ≤ t < t5]

At t4, S2 is turned off. Since iLr2 (t4 ) . 0 and iLr1 (t4 ) , 0, C2 is charged and C3 is discharged linearly. Since C2 and C3 < < Cr1 and Cr2, the inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drain-tosource voltage of S2 is limited by C2 and C3 such that S2 is turned off at ZVS. If the energy stored in Lr1, Lr2 and Lm1– Lm4 is greater than the energy stored in C2 and C3, then capacitor C3 can be discharged to zero voltage. The ZVS condition of S3 is given as

3.6

Lr + 2Lm

2 2 iLr1 t4 + iLr2 t4 ≥ Coss Vin2 /2

(2)

Mode 6 [t5 ≤ t < t6]

At t5, C3 is discharged to zero voltage. Since iLr2 (t5 ) . 0 and iLr1 (t5 ) , 0, the anti-parallel diode of S3 is conducting. Therefore S3 can be turned on at ZVS. The AC terminal voltages vab = Vin, vbc = 0, v p1 = Vin − vCr1 . 0 and v p2 = −vCr2 , 0. D1, D3, D6 and D8 are conducting in this mode. The magnetising voltages vLm1 = vLm2 = nVo and vLm3 = vLm4 = −nVo . Thus, iLm1 and iLm2 increase, and iLm3 and iLm4 decrease in this mode. In circuit 1, Lr1 and Cr1 IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

are resonant with the applied voltage Vin − 2nVo. In the same manner, Lr2 and Cr2 are resonant with the applied voltage 2nVo in circuit 2. Power is delivered from Vin to Ro through S1, S2, Cr1, Lr1, T1, T2, D1, D3 and Co in circuit 1. 3.7

Mode 7 [t6 ≤ t < t7]

At t6, S4 is turned off. Since iLr2 (t6 ) , 0 and iLr1 (t6 ) . 0, C1 is discharged linearly and C4 is charged linearly. The inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drain-to-source voltage of S4 is limited by C1 and C4 such that S4 is turned off at ZVS. If the energy stored in Lr1 and Lr2 is greater than the energy stored in C1 and C4, then C1 can be discharged to zero voltage. Thus, the ZVS condition of S1 is given as (3) Lr i2Lr1 t6 + i2Lr2 t6 ≥ Coss Vin2 /2 3.8

Mode 8 [t7 ≤ t < t8]

At t7, C1 is discharged to zero voltage. Since iLr2 (t7 ) , 0 and iLr1 (t7 ) . 0, the anti-parallel diode of S1 is conducting. Therefore S1 can be turned on at ZVS. The AC terminal voltages vab = vbc = Vin/2. Since D1, D3, D6 and D8 are still conducting in this mode, the magnetising voltages vLm1 = vLm2 = nVo and vLm3 = vLm4 = −nVo . Thus, iLm1 and iLm2 increase, and iLm3 and iLm4 decrease. In circuit 1, Lr1 and Cr1 are resonant with the applied voltage Vin/2 − 2nVo. In circuit 2, Lr2 and Cr2 are resonant with the applied voltage Vin/2 + 2nVo. The ﬂying capacitor voltage vCf = vCin1 = Vin /2. 3.9

Mode 9 [t8 ≤ t < t9]

At t8, iLm1 = iLm2 = iLr1 and iLm3 = iLm4 = iLr2 . Thus, D1– D8 are all in the off state. Cr1, Lr1, Lm1 and Lm2 in circuit 1 are resonant with the applied voltage Vin/2. In the same manner, Cr2, Lr2, Lm3 and Lm4 in circuit 2 are resonant with the applied voltage Vin/2. This mode ends at time t9 when S3 is turned off. 3.10

Mode 10 [t9 ≤ t < t0]

At t9, S3 is turned off. Since iLr2 (t9 ) , 0and iLr1 (t9 ) . 0, C2 is discharged and C3 is charged. The rising slope of the drain-to-source voltage of S3 is limited by C2 and C3 such that S3 is turned off at ZVS. If the energy stored in Lr1, Lr2 and Lm1–Lm4 is greater than the energy stored in C2 and C3, then C2 can be discharged to zero voltage. The ZVS condition of S2 is given as (4) Lr + 2Lm i2Lr1 t9 + i2Lr2 t9 ≥ Coss Vin2 /2 At t0, vS2,ds is decreased to zero voltage and the anti-parallel diode of S2 is conducting. Then, the circuit operations of the proposed converter in a switching period are completed.

4

Circuit characteristics

Since the charge and discharge times of C1–C4 can be neglected, only modes 1, 3, 4, 6, 8 and 9 are considered in the followings to derive the circuit characteristics of the proposed converter. In modes 1, 3, 6 and 8, the adopted 127

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www.ietdl.org converter is resonant at the series resonant frequency fr = 1/2p Lr Cr . In modes 4 and 9, the converter is resonant at the frequency fm = 1/2p Lr + 2Lm Cr . Since the maximum duty ratio of the AC terminal voltages vab and vbc is equal to 0.5, the AC voltage gain of the adopted resonant converter at the selected switching frequency can be expressed in (21) based on the fundamental frequency analysis 2VLm ,f G f = ac s Vab,f

2

2 = 1/ 1 + k 1 − fr2 /fs2 +Q2 fs /fr − fr /fs (5) Where k = Lr/(2Lm), Rac = 32n 2Ro/π 2 fr = 1/2p Lr Cr ,

⎡

⎤ 2 2 C V C V oss in in Lr,min =max⎣ oss 2 , 2 2 −2Lm ⎦ 2 2 iLr1 t1 +iLr2 t1 2 iLr1 t4 +iLr2 t4 (9) Since iLr1 t4 = iLr2 t4 = Im , the minimum resonant inductance can be rewritten as ⎡ C Vin2 Lr, min = max⎣ oss , 2 i2Lr1 t1 + i2Lr2 t1

⎤ 4Coss L2m fr2 Vin2 2 − 2Lm ⎦ n 2 Vo + VD (10)

Q = Zo / 2Rac = Lr /Cr / 2Rac

and fs is the switching frequency. The maximum DC voltage gain of the proposed converter at the minimum input voltage case can be expressed as Gdc,max = 4n Vo + Vf /Vin,min

The necessary resonant inductor Lr to achieve ZVS turn-on for S1–S4 is obtained from (1) and (2)

(6)

where Vf is the voltage drop on D1–D8. If the duty ratio at AC terminal voltages vab and vbc is less than 0.5, then the voltage gain of the proposed converter is less than Gdc,max. The voltage gain of the proposed converter depends on the duty cycle, initial resonant inductor current and initial resonant capacitor voltage and it is a nonlinear function between the output voltage, duty ratio, load current and input voltage. Thus, it is not easy to obtain the voltage conversion ratio at steady state. If the duty cycle of the AC terminal voltage vab is equal to 0.5, the AC voltage gain of the proposed converter at the operating switching frequency can be obtained from (5) with the given parameters k, Q, fs and fr. Thus, the turns ratio of the isolated transformers T1–T4 can be obtained from (5) and (6) Gdc,max Vin,min Gac fs Vin,min = n= 4 Vo + Vf 4 Vo + Vf

The average voltages of Cr1, Cr2 and Cf are equal to Vin/2. The voltage stress of all switches is equal to Vin/2 in the proposed converter. The voltage stress and the average current of rectiﬁer diodes D1–D8 are equal to 2(Vo + Vf ) and Io/8, respectively.

5

Design example and test results

The circuit speciﬁcations of a scale-down prototype are: Vin = 550–600 V, Vo = 24 V, Po,rated = 1 kW, series resonant frequency fr = 125 kHz, switching frequency fs = 100 kHz, k = 0.14 and Q = 0.2. The turns ratio of T1–T4 is expressed as (see eqn (10)) The primary and secondary winding turns of T1–T4 are 30 and 5 turns, respectively. The AC equivalent resistance Rac at full load is obtained as Rac = 32n2 Ro /p2 = 32 × 62 × 242 /1000 /3.141592 ≃ 67 V

The series resonant inductance and resonant capacitance are obtained as

Vin,min = 2

2 1 + k 1 − fr2 /fs2 4 Vo + Vf +Q2 fs /fr − fr /fs (7)

0.2 × 67 ≃ 34 mH (13) Lr = QRac / pfr = p125 000 Cr = 1/ 4p2 Lr fr2 = 1/ 4p2 34 × 10−6 × 125 0002 ≃ 48 nF

The selected switching frequency fs is less than the series resonant frequency fr. Thus, active switches can be turned on at ZVS and rectiﬁer diodes are turned off at ZCS. If the duty cycle of vab and vbc is equal to 0.5, the peak magnetising current Im can be expressed as Im = n Vo + VD / 4Lm fr

(8)

(14)

The magnetising inductances of T1–T4 are given as Lm = Lr /(2k) = 34/(2 × 0.14) ≃ 121 mH

(15)

The capacitance of Cf is 0.4 μF. The output capacitance Co is 5400 μF. The voltage stress and average current of rectiﬁer

Vin, min n=

2 2 1 + k 1 − fr2 /fs2 4 Vo + Vf +Q2 fs /fr − fr /fs 550 = 2 ≃ 6 2 +0.22 (100/125) − (125/100) 4 × (24 + 0.78) 1 + 0.14 × 1 − 1252 /1002 128 & The Institution of Engineering and Technology 2013

(12)

(11)

IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org diodes D1–D8 are given as vD, max = 2 Vo + Vf = 2(24 + 0.78) = 49.56 V iD,av = Io, max /8 ≃ 5.2 A

(16) (17)

Thus, the fast recovery diodes 30CPQ150 with 150 V voltage rating, 30 A current rating and 0.78 V voltage drop are used for D1–D8. The voltage stress of power switches S1–S4 is equal to 300 V. The available commercial MOSFET with at least 300 V voltage rating for power switches S1–S4 is IRFP460 which has 500 V voltage rating and 20 A current rating. The fast recovery diodes 30ETH06 with 600 V voltage rating and 30 A current rating are used for clamped diodes Da and Db. The phase-shift PWM IC UC3895 is used to generate PWM signals for S1–S4 and to regulate the output voltage. Based on the derived circuit parameters in the previous section, experimental results are presented to verify the effectiveness of the proposed converter. Fig. 4 shows the measured waveforms of the PWM signals of S1–S4 at full load with the different input voltages. S2 and S3 are phase-shifted with respective to S1 and S4, respectively. The high input voltage has more phase-shift angle between S1 and S2. The measured gate voltage, drain voltage and switch current of S1 at 25% load and the different input voltages are shown in Fig. 5. Since the operation behaviours of S4 are similar to the PWM waveforms of S1, the curves in Fig. 5 are also valid for switch S4. In the same manner, the measured gate voltage, drain voltage and switch current of S2 at 25% load and the different input voltages are given in Fig. 6. The curves in Fig. 6 are also

Fig. 5 Measured results of the gate voltage, drain voltage and switch current of S1 at 25% load a Vin = 550 V b Vin = 600 V

Fig. 6 Measured results of the gate voltage, drain voltage and switch current of S2 at 25% load a Vin = 550 V b Vin = 600 V

Fig. 4 Measured waveforms of the PWM signals of S1–S4 at full load a Vin = 550 V b Vin = 600 V IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

Fig. 7 Measured results of the resonant capacitor voltages, AC side voltages and resonant inductor currents at full load and Vin = 600 V 129

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www.ietdl.org full load are illustrated in Fig. 7. There are three voltage levels, 0, Vin/2 and Vin, on the AC terminal voltages vab and vbc. When AC side voltage vab = Vin (or vbc = 0), vCr1 and iLr1 increase and vCr2 and iLr2 decrease. On the other hand, vCr1 and iLr1 decrease and vCr2 and iLr2 increase if vab = 0 (or vbc = Vin). Fig. 8 gives the experimental waveforms of the gate voltages, clamped diode currents, ﬂying capacitor current and switch currents at full load. The experimental waveforms of the gate voltages and the output currents of four centre-tapped rectiﬁers at full load and different input voltages are shown in Fig. 9. It is clear that diodes D1–D8 are all turned off at ZCS and there is no reverse recovery loss on rectiﬁer diodes. The output currents of four centre-tapped rectiﬁers are balanced under the test results.

Fig. 8 Measured results of the gate voltages, clamped diode currents, ﬂying capacitor current and switching currents at full load and Vin = 600 V

valid for switch S3 because the operation behaviours of S3 are similar to the PWM waveforms of S2. The ZVS conditions of power switches S1–S4 at high load are easier to be implemented than the ZVS condition of S1–S4 at light load. From Figs. 5 and 6, it can be obtained that S1–S4 are all turned on at ZVS from 25% loads and the voltage stress of S1–S4 is equal to Vin/2. The measured resonant capacitor voltages, AC side voltages and resonant inductor currents at

6

Conclusions

A new ZVS three-level DC converter is presented for high input voltage and high load current applications. In the proposed circuit, two three-level PWM circuits with the same power switches are adopted to reduce the input side current ripple and reduce the switch counts compared to the conventional three-level PWM converter. In order to reduce the current rating of transformer windings and the rectiﬁer diodes, four centre-tapped rectiﬁers are connected in parallel at the secondary side for high load current applications. The duty cycle PWM control is adopted to regulate the output voltage. Since the selected switching frequency is lower than the series resonant frequency by resonant inductance and resonant capacitance, power MOSFETs can be turned on at ZVS and rectiﬁer diodes can be turned off at ZCS. Thus, the switching losses on power semiconductors are reduced. If the circuit parameters of the resonant components are not matched such as temperature and device tolerances, the output currents io1 and io2 are not balanced. However, the unbalanced output currents can be controlled below the allowed tolerance level by using the same circuit parameters. Finally, experiments based on a laboratory prototype with output current scale-down verifying the effectiveness of the converter are described.

8

Acknowledgment

This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224-022 -MY3.

9

Fig. 9 Measured results of the gate voltages and the out currents of each diode rectiﬁer at full load a Vin = 550 V b Vin = 600 V 130 & The Institution of Engineering and Technology 2013

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www.ietdl.org 7 Chu, E., Hou, X., Zhang, H., Wu, M., Liu, X.: ‘Novel zero-voltage and zero-current switching (ZVZCS) PWM three-level DC/DC converter using output coupled inductor’. IEEE Trans. Power Electron., 2013, in press 8 Lin, B.-R., Liu, C.-H.: ‘ZVS DC/DC converter based on two three-level PWM circuits sharing the same power switches’, IEEE Trans. Ind. Electron., 2013, 60, (10), pp. 4191–4200 9 Lin, B.R., Hou, B.R.: ‘Analysis of a zero voltage switching DC/DC converter without output inductor’, IET Proc. – Power Electron., 2012, 5, (6), pp. 790–800 10 Ruan, X., Xu, D., Zhou, L., Li, B., Chen, Q.: ‘Zero-voltage-switching PWM three-level converter with two clamping diodes’, IEEE Trans. Ind. Electron., 2002, 49, (4), pp. 790–799 11 Jin, K., Ruan, X., Liu, F.: ‘An improved ZVS PWM three-level converter’, IEEE Trans. Ind. Electron., 2007, 54, (1), pp. 319–329 12 Liu, F., Ruan, X.: ‘ZVS combined three-level converter—A topology suitable for high input voltage with wide range applications’, IEEE Trans. Ind. Electron., 2007, 54, (2), pp. 1061–1072 13 Canales, F., Barbosa, P.M., Lee, F.C.: ‘A zero voltage and zero current switching three level dc/dc converter’, IEEE Trans. Power Electron., 2002, 17, (6), pp. 898–964 14 Deschamps, E., Barbi, I.: ‘A ﬂying-capacitor ZVS PWM 1.5 kW dc-to-dc converter with half of the input voltage across the switches’, IEEE Trans. Power Electron., 2000, 15, (5), pp. 855–860 15 Barbi, I., Gules, R., Redl, R., Sokal, N.O.: ‘DC-DC converter: four switches Vpk = Vin/2, capacitive turn-off snubbering, ZVS turn-on’, IEEE Trans. Power Electron., 2004, 19, (4), pp. 918–927 16 Song, T.T., Huang, N., Ioinovici, A.: ‘A family of zero-voltage and zero-current-switching (ZVZCS) three-level dc–dc converters with secondary-assisted regenerative passive snubber’, IEEE Trans. Circuits Syst., 2005, 52, (11), pp. 2473–2481

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17 Chen, W., Ruan, X.: ‘Zero-voltage-switching PWM hybrid full-bridge three-level converter with secondary-voltage clamping scheme’, IEEE Trans. Ind. Electron., 2008, 55, (2), pp. 644–654 18 Lin, B.R., Wu, S.F.: ‘Implementation of a series resonant converter with series–parallel transformers’, IET Proc. – Power Electron., 2011, 4, (8), pp. 919–926 19 Beiranvand, R., Rashidian, B., Zolghadri, M.R., Alavi, S.M.H.: ‘Using LLC resonant converter for designing wide-range voltage source’, IEEE Trans. Ind. Electron., 2011, 58, (5), pp. 1746–1756 20 Lin, B.R., Dong, J.Y.: ‘ZVS resonant converter with parallel–series transformer connection’, IEEE Trans. Ind. Electron., 2011, 58, (7), pp. 2972–2979 21 Yang, B., Lee, F.C., Zhang, A.J., Huang, G.: ‘LLC resonant converter for front end DC/DC conversion’, Proc. IEEE APEC, 2002, 2, pp. 1108–1112 22 Liu, F., Yan, J., Ruan, X.: ‘Zero-voltage and zero-currents witching PWM combined three-level dc/dc converter’, IEEE Trans. Ind. Electron., 2010, 57, (5), pp. 1644–1654 23 Xie, X., Zhang, J., Zhao, C., Zhao, Z., Qian, Z.: ‘Analysis and optimization of LLC resonant converter with a novel over-current protection circuit’, IEEE Trans. Power Electron., 2007, 22, (2), pp. 435–443 24 Gu, Y., Lu, Z., Qian, Z.: ‘Three level LLC series resonant DC/DC converter’. Proc. of IEEE APEC Conf., 2004, pp. 1647–1652 25 Lin, B.-R., Cheng, P.-J.: ‘New ZVS DC-DC converter with series-connected transformers to balance the output currents’. IEEE Trans. Power Electron., 2014, 29, (1), pp. 246–255 26 Jin, K., Ruan, X.: ‘Hybrid full-bridge three-level LLC resonant converter—a novel DC–DC converter suitable for fuel-cell power system’, IEEE Trans. Ind. Electron., 2006, 53, (5), pp. 1492–1503

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ISSN 1755-4535

Zero voltage switching DC converter for high-input voltage and high-load current applications Bor-Ren Lin, Chih-Chieh Chen Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou City, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: A new DC/DC pulse-width modulation (PWM) converter with the functions of zero voltage switching (ZVS) for power switches and zero current switching (ZCS) for rectiﬁer diodes is presented for high-input voltage and high-load current applications. Three-level PWM circuit with two clamped diodes and one ﬂying capacitor is adopted to achieve ZVS turn-on for all power switches, to balance two input capacitor voltages and to limit the voltage rating of each switch at one-half of input voltage. Two three-level PWM circuits with the same power switches are used to share the load current for medium power applications. Series–parallel resonant converter or LLC (Lr, Lm and Cr) converter is adopted to achieve ZCS turn-off for rectiﬁer diodes. Thus, the switching losses of power switches are reduced and the reverse recovery losses of rectiﬁer diodes are eliminated. In order to high load current application, four centre-tapped rectiﬁers are connected in parallel to reduce the current rating of rectiﬁer diodes and transformer windings. Experiments are provided to verify the effectiveness of the proposed converter.

1

Introduction

For three-phase systems such as 380 Vrms or 480 Vrms, a diode rectiﬁer with power factor correction (PFC) is generally used in the front stage to reduce the line current harmonics in order to meet the international standard IEC 61000-3-2 or IEEE 519 and to provide a high DC bus voltage. Generally, the DC bus voltage of the three-phase AC/DC converter with/without PFC is in the range of 530–800 V. Thus, the voltage rating of power switches in the second stage DC/DC converter such as phase-shift full bridge converter should be greater than 800 V. In order to use low voltage rating metal oxide semiconductor ﬁeld effect transistors (MOSFETs) (600 V) with high switching frequency instead of high-voltage rating IGBT (1200 V) in the second stage DC converter with high frequency and high-power density demand, three-level or multilevel converters [1–4] have been proposed as the DC/DC converters for high input voltage applications. Three-level zero voltage switching (ZVS) converters [5–17] have been proposed to reduce the switching losses at the desired load range. The basic three-level diode clamped DC converter has been discussed in [5–9]. In [10–12], the additional auxiliary circuit is added in the three-level diode clamped converter to extend the ZVS range. In [13– 17], a ﬂying capacitor is added in the primary side to balance two input capacitor voltages and an active circuit is added in the secondary side to achieve zero current switching (ZCS) turn-off of rectiﬁer diodes. However, the ZVS of these topologies are not wide or full load range 124 & The Institution of Engineering and Technology 2013

and rectiﬁer diodes have reverse recovery losses. Two-level LLC converters [18–21] can achieve ZVS turn on for power switches and ZCS turn off for rectiﬁer diodes within a wide range of input voltage and load conditions. However, the voltage stress of active switches in these circuit topologies is equal to input voltage. For high input voltage applications, three-level LLC converter is presented in [22–26]. However, the more power switches are used in [26] and the current stress at the secondary side in these circuit topologies is high for heavy load condition. It is a better way to use parallel connection at the secondary side for high load current application in order to reduce the current rating of rectiﬁer diodes and transformer windings. A new DC/DC converter with ZVS/ZCS is presented for high input voltage and medium power applications. In order to use power semiconductors with low-voltage rating in high input voltage applications, three-level DC converter with two clamped diodes and one ﬂying capacitor is adopted in the proposed circuit. Thus, the voltage at each power switch is clamped at one-half of input voltage and two input capacitor voltages are automatically balanced through a ﬂying capacitor. Two three-level pulse-width modulation (PWM) circuits with the same power switches are used to share the load current for medium power applications. Thus, the switch counts in the proposed converter are less than the conventional parallel three-level converter with eight power switches. The LLC converter is used in the primary side of transformer in order to achieve ZVS turn on for all switches and ZCS IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org turn off for rectiﬁer diodes if the switching frequency is less than the series resonant frequency. The switching loss of MOSFETs and the reverse recovery loss of diodes are eliminated. The PWM control instead of frequency modulation (FM) control is used to regulate output voltage. Four centre-tapped rectiﬁers are connected in parallel to reduce the current rating of rectiﬁer diodes and transformer windings for high load current application. The primary windings are connected in series in order to balance the secondary side currents. Finally, experiments based on a laboratory prototype are provided to verify the operation principle of the proposed converter.

2

Circuit configuration

Fig. 1 shows the circuit conﬁguration of the proposed converter for high input voltage (Vin = 600 V) and high output current applications. There are two three-level ZVS circuits connected in parallel in the proposed converter. The ﬁrst three-level circuit includes Cin1, Cin2, Da, Db, Cf, S1–S4, C1–C4, Cr1, Lr1, T1–T2, D1–D4, Co and Ro. The second three-level circuit includes the components of Cin1, Cin2, Da, Db, Cf, S1–S4, C1–C4, Cr2, Lr2, T3–T4, D5–D8, Co and Ro. Input capacitances Cin1 and Cin2 are equal and large enough to be two input voltage sources vCin1 = vCin2 = Vin/2. S1–S4 are power MOSFETs stressed with Vin/2. C1–C4 are the output capacitances of S1–S4, respectively. Da and Db are the clamped diodes. Cf is a ﬂying capacitor with the average voltage of Vin/2. Cr1 and Cr2 are the series resonant capacitances and the average capacitor voltages VCr1 = VCr2 = Vin /2. Lr1 and Lr2 are the series resonant inductances. Lm1–Lm4 are the magnetising inductances of transformers T1–T4, respectively. D1–D8 are the rectiﬁer diodes. Ro is the load resistance and Co is the output capacitance. Two three-level circuits share the same power switches S1–S4, the clamped diodes Da and Db, and the ﬂying capacitor Cf. In each three-level circuit, two transformers are connected in series at the primary side and connected in parallel at the secondary side to balance the secondary side currents for high output current applications. The PWM signals of S1 and S4 are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of S2 and S3 are complementary each other. Based on the on/off states of S1–S4, three voltage levels Vin, Vin/2 and 0 are generated on the AC terminal voltages vab and vbc. Since the average voltages of Cr1 and Cr2 are all equal to Vin/2, the other three voltage levels Vin/2, 0 and –Vin/2 are generated on the terminal voltages vp1 and vp2. Each centre-tapped rectiﬁer supplies one-fourth of load current such that the current rating of each transformer secondary winding and the rectiﬁer diodes are reduced.

Fig. 1 Circuit conﬁguration of the proposed converter IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

3

Operation principle

Fig. 2 illustrates the key PWM waveforms of the proposed converter. The duty cycle of switches S1–S4 is equal to 0.5. The PWM signals of S2 and S3 are phase-shifted with respective to the PWM signals of S1 and S4, respectively. The phase-shift PWM scheme is adopted to regulate the output voltage against the input voltage and load current variations. The following system analysis is based on the assumptions of (i) VCin1 and VCin2 are two balanced voltage sources, (ii) C1 = C2 = C3 = C4 = Coss, Cr1 = Cr2 = Cr and Cr > Coss, (iii) VCr1 = VCr2 = VCf = Vin /2, (iv) Vo is a constant output voltage, (v) Lm1 = Lm2 = Lm3 = Lm4 = Lm, Lr1 = Lr2 = Lr and Lr ≪ Lm , (vi) the turns ratio of transformers T1–T4 is n = np/ns1 = np/ns2 and (vii) MOSFETs S1–S4 and diodes D1–D8 and Da–Db are ideal. Based on the on/off states of S1–S4, Da–Db and D1–D8, there are ten operating modes in the proposed converter during one switching period. The equivalent circuits of these operating modes are shown in Fig. 3. Prior to t0, S1 is conducting and inductor currents iLr1 . 0 and iLr2 , 0. 3.1

Mode 1 [t0 ≤ t < t1]

At t0, C2 is discharged to zero voltage. Since iLr2 (t0 ) − iLr1 (t0 ) , 0, the anti-parallel diode of S2 is conducting and switch S2 can be turned on at this moment to achieve ZVS. The AC terminal voltages vab = 0 and vbc = Vin. The primary side voltage vp1 = –vCr1 < 0 and vp2 = Vin–vCr2 > 0 such that D2 and D4 in the ﬁrst three-level circuit and D5 and D7 in the second three-level circuit are conducting. The magnetising inductor voltages vLm1 = vLm2 = −nVo and vLm3 = vLm4 = nVo .

Fig. 2 Key waveforms of the proposed converter 125

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www.ietdl.org

Fig. 3 Operation modes of the proposed converter during one switching cycle a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10

The magnetising currents iLm1 and iLm2 decrease and iLm3 and iLm4 increase in this mode. Lr1 and Cr1 in the ﬁrst circuit are resonant with the applied voltage 2nVo. Lr2 and Cr2 in the 126 & The Institution of Engineering and Technology 2013

second circuit are resonant with the applied voltage Vin − 2nVo. Power is transferred from Vin to Ro through S1, S2, T3, T4, Lr2, Cr2, D5, D7 and Co. In ﬁrst circuit, the energy stored in IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org Lr1 and Cr1 is transferred to output load Ro through S1, S2, Cr1, Lr1, T1, T2, D2, D4 and Co. 3.2

Mode 2 [t1 ≤ t < t2]

At t1, S1 is turned off. Since iLr2 (t1 ) . 0and iLr1 (t1 ) , 0, C1 is charged and C4 is discharged linearly. Since C1 and C4 < < Cr1 and Cr2, the inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drainto-source voltage of S1 is limited by C1 and C4 such that S1 is turned off at ZVS. If the energy stored in Lr1 and Lr2 is greater than the energy stored in C1 and C4, then C4 can be discharged to zero voltage. The ZVS condition of S4 is given as Lr (i2Lr1 (t1 ) + i2Lr2 (t1 )) ≥ Coss Vin2 /2 3.3

(1)

Mode 3 [t2 ≤ t < t3]

At t2, C4 is discharged to zero voltage. Since iLr2 (t2 ) . 0 and iLr1 (t2 ) , 0, the anti-parallel diode of S4 is conducting. Therefore S4 can be turned on at this moment to achieve ZVS. The AC terminal voltages vab = vbc = Vin/2. The rectiﬁer diodes D2, D4, D5 and D7 are still conducting in this mode. The magnetising inductor voltages vLm1 = vLm2 = −nVo and vLm3 = vLm4 = nVo such that the magnetising currents iLm1 and iLm2 decrease and iLm3 and iLm4 increase. Lr1 and Cr1 in circuit 1 are resonant with the applied voltage Vin/ 2 + 2nVo and Lr2 and Cr2 in circuit 2 are resonant with the applied voltage Vin/2 − 2nVo. In this mode, the ﬂying capacitor voltage vCf = vCin2 = Vin /2. 3.4

Mode 4 [t3 ≤ t < t4]

At t3, iLm1 = iLm2 = iLr1 and iLm3 = iLm4 = iLr2 such that the rectiﬁer diodes D1–D8 are all in the off-state. Cr1, Lr1, Lm1 and Lm2 in circuit 1 are resonant with the applied voltage Vin/2. In the same manner, Cr2, Lr2, Lm3 and Lm4 in circuit 2 are resonant with the applied voltage Vin/2. 3.5

Mode 5 [t4 ≤ t < t5]

At t4, S2 is turned off. Since iLr2 (t4 ) . 0 and iLr1 (t4 ) , 0, C2 is charged and C3 is discharged linearly. Since C2 and C3 < < Cr1 and Cr2, the inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drain-tosource voltage of S2 is limited by C2 and C3 such that S2 is turned off at ZVS. If the energy stored in Lr1, Lr2 and Lm1– Lm4 is greater than the energy stored in C2 and C3, then capacitor C3 can be discharged to zero voltage. The ZVS condition of S3 is given as

3.6

Lr + 2Lm

2 2 iLr1 t4 + iLr2 t4 ≥ Coss Vin2 /2

(2)

Mode 6 [t5 ≤ t < t6]

At t5, C3 is discharged to zero voltage. Since iLr2 (t5 ) . 0 and iLr1 (t5 ) , 0, the anti-parallel diode of S3 is conducting. Therefore S3 can be turned on at ZVS. The AC terminal voltages vab = Vin, vbc = 0, v p1 = Vin − vCr1 . 0 and v p2 = −vCr2 , 0. D1, D3, D6 and D8 are conducting in this mode. The magnetising voltages vLm1 = vLm2 = nVo and vLm3 = vLm4 = −nVo . Thus, iLm1 and iLm2 increase, and iLm3 and iLm4 decrease in this mode. In circuit 1, Lr1 and Cr1 IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

are resonant with the applied voltage Vin − 2nVo. In the same manner, Lr2 and Cr2 are resonant with the applied voltage 2nVo in circuit 2. Power is delivered from Vin to Ro through S1, S2, Cr1, Lr1, T1, T2, D1, D3 and Co in circuit 1. 3.7

Mode 7 [t6 ≤ t < t7]

At t6, S4 is turned off. Since iLr2 (t6 ) , 0 and iLr1 (t6 ) . 0, C1 is discharged linearly and C4 is charged linearly. The inductor currents iLr1 and iLr2 are almost constant in this mode. The rising slope of the drain-to-source voltage of S4 is limited by C1 and C4 such that S4 is turned off at ZVS. If the energy stored in Lr1 and Lr2 is greater than the energy stored in C1 and C4, then C1 can be discharged to zero voltage. Thus, the ZVS condition of S1 is given as (3) Lr i2Lr1 t6 + i2Lr2 t6 ≥ Coss Vin2 /2 3.8

Mode 8 [t7 ≤ t < t8]

At t7, C1 is discharged to zero voltage. Since iLr2 (t7 ) , 0 and iLr1 (t7 ) . 0, the anti-parallel diode of S1 is conducting. Therefore S1 can be turned on at ZVS. The AC terminal voltages vab = vbc = Vin/2. Since D1, D3, D6 and D8 are still conducting in this mode, the magnetising voltages vLm1 = vLm2 = nVo and vLm3 = vLm4 = −nVo . Thus, iLm1 and iLm2 increase, and iLm3 and iLm4 decrease. In circuit 1, Lr1 and Cr1 are resonant with the applied voltage Vin/2 − 2nVo. In circuit 2, Lr2 and Cr2 are resonant with the applied voltage Vin/2 + 2nVo. The ﬂying capacitor voltage vCf = vCin1 = Vin /2. 3.9

Mode 9 [t8 ≤ t < t9]

At t8, iLm1 = iLm2 = iLr1 and iLm3 = iLm4 = iLr2 . Thus, D1– D8 are all in the off state. Cr1, Lr1, Lm1 and Lm2 in circuit 1 are resonant with the applied voltage Vin/2. In the same manner, Cr2, Lr2, Lm3 and Lm4 in circuit 2 are resonant with the applied voltage Vin/2. This mode ends at time t9 when S3 is turned off. 3.10

Mode 10 [t9 ≤ t < t0]

At t9, S3 is turned off. Since iLr2 (t9 ) , 0and iLr1 (t9 ) . 0, C2 is discharged and C3 is charged. The rising slope of the drain-to-source voltage of S3 is limited by C2 and C3 such that S3 is turned off at ZVS. If the energy stored in Lr1, Lr2 and Lm1–Lm4 is greater than the energy stored in C2 and C3, then C2 can be discharged to zero voltage. The ZVS condition of S2 is given as (4) Lr + 2Lm i2Lr1 t9 + i2Lr2 t9 ≥ Coss Vin2 /2 At t0, vS2,ds is decreased to zero voltage and the anti-parallel diode of S2 is conducting. Then, the circuit operations of the proposed converter in a switching period are completed.

4

Circuit characteristics

Since the charge and discharge times of C1–C4 can be neglected, only modes 1, 3, 4, 6, 8 and 9 are considered in the followings to derive the circuit characteristics of the proposed converter. In modes 1, 3, 6 and 8, the adopted 127

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www.ietdl.org converter is resonant at the series resonant frequency fr = 1/2p Lr Cr . In modes 4 and 9, the converter is resonant at the frequency fm = 1/2p Lr + 2Lm Cr . Since the maximum duty ratio of the AC terminal voltages vab and vbc is equal to 0.5, the AC voltage gain of the adopted resonant converter at the selected switching frequency can be expressed in (21) based on the fundamental frequency analysis 2VLm ,f G f = ac s Vab,f

2

2 = 1/ 1 + k 1 − fr2 /fs2 +Q2 fs /fr − fr /fs (5) Where k = Lr/(2Lm), Rac = 32n 2Ro/π 2 fr = 1/2p Lr Cr ,

⎡

⎤ 2 2 C V C V oss in in Lr,min =max⎣ oss 2 , 2 2 −2Lm ⎦ 2 2 iLr1 t1 +iLr2 t1 2 iLr1 t4 +iLr2 t4 (9) Since iLr1 t4 = iLr2 t4 = Im , the minimum resonant inductance can be rewritten as ⎡ C Vin2 Lr, min = max⎣ oss , 2 i2Lr1 t1 + i2Lr2 t1

⎤ 4Coss L2m fr2 Vin2 2 − 2Lm ⎦ n 2 Vo + VD (10)

Q = Zo / 2Rac = Lr /Cr / 2Rac

and fs is the switching frequency. The maximum DC voltage gain of the proposed converter at the minimum input voltage case can be expressed as Gdc,max = 4n Vo + Vf /Vin,min

The necessary resonant inductor Lr to achieve ZVS turn-on for S1–S4 is obtained from (1) and (2)

(6)

where Vf is the voltage drop on D1–D8. If the duty ratio at AC terminal voltages vab and vbc is less than 0.5, then the voltage gain of the proposed converter is less than Gdc,max. The voltage gain of the proposed converter depends on the duty cycle, initial resonant inductor current and initial resonant capacitor voltage and it is a nonlinear function between the output voltage, duty ratio, load current and input voltage. Thus, it is not easy to obtain the voltage conversion ratio at steady state. If the duty cycle of the AC terminal voltage vab is equal to 0.5, the AC voltage gain of the proposed converter at the operating switching frequency can be obtained from (5) with the given parameters k, Q, fs and fr. Thus, the turns ratio of the isolated transformers T1–T4 can be obtained from (5) and (6) Gdc,max Vin,min Gac fs Vin,min = n= 4 Vo + Vf 4 Vo + Vf

The average voltages of Cr1, Cr2 and Cf are equal to Vin/2. The voltage stress of all switches is equal to Vin/2 in the proposed converter. The voltage stress and the average current of rectiﬁer diodes D1–D8 are equal to 2(Vo + Vf ) and Io/8, respectively.

5

Design example and test results

The circuit speciﬁcations of a scale-down prototype are: Vin = 550–600 V, Vo = 24 V, Po,rated = 1 kW, series resonant frequency fr = 125 kHz, switching frequency fs = 100 kHz, k = 0.14 and Q = 0.2. The turns ratio of T1–T4 is expressed as (see eqn (10)) The primary and secondary winding turns of T1–T4 are 30 and 5 turns, respectively. The AC equivalent resistance Rac at full load is obtained as Rac = 32n2 Ro /p2 = 32 × 62 × 242 /1000 /3.141592 ≃ 67 V

The series resonant inductance and resonant capacitance are obtained as

Vin,min = 2

2 1 + k 1 − fr2 /fs2 4 Vo + Vf +Q2 fs /fr − fr /fs (7)

0.2 × 67 ≃ 34 mH (13) Lr = QRac / pfr = p125 000 Cr = 1/ 4p2 Lr fr2 = 1/ 4p2 34 × 10−6 × 125 0002 ≃ 48 nF

The selected switching frequency fs is less than the series resonant frequency fr. Thus, active switches can be turned on at ZVS and rectiﬁer diodes are turned off at ZCS. If the duty cycle of vab and vbc is equal to 0.5, the peak magnetising current Im can be expressed as Im = n Vo + VD / 4Lm fr

(8)

(14)

The magnetising inductances of T1–T4 are given as Lm = Lr /(2k) = 34/(2 × 0.14) ≃ 121 mH

(15)

The capacitance of Cf is 0.4 μF. The output capacitance Co is 5400 μF. The voltage stress and average current of rectiﬁer

Vin, min n=

2 2 1 + k 1 − fr2 /fs2 4 Vo + Vf +Q2 fs /fr − fr /fs 550 = 2 ≃ 6 2 +0.22 (100/125) − (125/100) 4 × (24 + 0.78) 1 + 0.14 × 1 − 1252 /1002 128 & The Institution of Engineering and Technology 2013

(12)

(11)

IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

www.ietdl.org diodes D1–D8 are given as vD, max = 2 Vo + Vf = 2(24 + 0.78) = 49.56 V iD,av = Io, max /8 ≃ 5.2 A

(16) (17)

Thus, the fast recovery diodes 30CPQ150 with 150 V voltage rating, 30 A current rating and 0.78 V voltage drop are used for D1–D8. The voltage stress of power switches S1–S4 is equal to 300 V. The available commercial MOSFET with at least 300 V voltage rating for power switches S1–S4 is IRFP460 which has 500 V voltage rating and 20 A current rating. The fast recovery diodes 30ETH06 with 600 V voltage rating and 30 A current rating are used for clamped diodes Da and Db. The phase-shift PWM IC UC3895 is used to generate PWM signals for S1–S4 and to regulate the output voltage. Based on the derived circuit parameters in the previous section, experimental results are presented to verify the effectiveness of the proposed converter. Fig. 4 shows the measured waveforms of the PWM signals of S1–S4 at full load with the different input voltages. S2 and S3 are phase-shifted with respective to S1 and S4, respectively. The high input voltage has more phase-shift angle between S1 and S2. The measured gate voltage, drain voltage and switch current of S1 at 25% load and the different input voltages are shown in Fig. 5. Since the operation behaviours of S4 are similar to the PWM waveforms of S1, the curves in Fig. 5 are also valid for switch S4. In the same manner, the measured gate voltage, drain voltage and switch current of S2 at 25% load and the different input voltages are given in Fig. 6. The curves in Fig. 6 are also

Fig. 5 Measured results of the gate voltage, drain voltage and switch current of S1 at 25% load a Vin = 550 V b Vin = 600 V

Fig. 6 Measured results of the gate voltage, drain voltage and switch current of S2 at 25% load a Vin = 550 V b Vin = 600 V

Fig. 4 Measured waveforms of the PWM signals of S1–S4 at full load a Vin = 550 V b Vin = 600 V IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 124–131 doi: 10.1049/iet-pel.2013.0128

Fig. 7 Measured results of the resonant capacitor voltages, AC side voltages and resonant inductor currents at full load and Vin = 600 V 129

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www.ietdl.org full load are illustrated in Fig. 7. There are three voltage levels, 0, Vin/2 and Vin, on the AC terminal voltages vab and vbc. When AC side voltage vab = Vin (or vbc = 0), vCr1 and iLr1 increase and vCr2 and iLr2 decrease. On the other hand, vCr1 and iLr1 decrease and vCr2 and iLr2 increase if vab = 0 (or vbc = Vin). Fig. 8 gives the experimental waveforms of the gate voltages, clamped diode currents, ﬂying capacitor current and switch currents at full load. The experimental waveforms of the gate voltages and the output currents of four centre-tapped rectiﬁers at full load and different input voltages are shown in Fig. 9. It is clear that diodes D1–D8 are all turned off at ZCS and there is no reverse recovery loss on rectiﬁer diodes. The output currents of four centre-tapped rectiﬁers are balanced under the test results.

Fig. 8 Measured results of the gate voltages, clamped diode currents, ﬂying capacitor current and switching currents at full load and Vin = 600 V

valid for switch S3 because the operation behaviours of S3 are similar to the PWM waveforms of S2. The ZVS conditions of power switches S1–S4 at high load are easier to be implemented than the ZVS condition of S1–S4 at light load. From Figs. 5 and 6, it can be obtained that S1–S4 are all turned on at ZVS from 25% loads and the voltage stress of S1–S4 is equal to Vin/2. The measured resonant capacitor voltages, AC side voltages and resonant inductor currents at

6

Conclusions

A new ZVS three-level DC converter is presented for high input voltage and high load current applications. In the proposed circuit, two three-level PWM circuits with the same power switches are adopted to reduce the input side current ripple and reduce the switch counts compared to the conventional three-level PWM converter. In order to reduce the current rating of transformer windings and the rectiﬁer diodes, four centre-tapped rectiﬁers are connected in parallel at the secondary side for high load current applications. The duty cycle PWM control is adopted to regulate the output voltage. Since the selected switching frequency is lower than the series resonant frequency by resonant inductance and resonant capacitance, power MOSFETs can be turned on at ZVS and rectiﬁer diodes can be turned off at ZCS. Thus, the switching losses on power semiconductors are reduced. If the circuit parameters of the resonant components are not matched such as temperature and device tolerances, the output currents io1 and io2 are not balanced. However, the unbalanced output currents can be controlled below the allowed tolerance level by using the same circuit parameters. Finally, experiments based on a laboratory prototype with output current scale-down verifying the effectiveness of the converter are described.

8

Acknowledgment

This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224-022 -MY3.

9

Fig. 9 Measured results of the gate voltages and the out currents of each diode rectiﬁer at full load a Vin = 550 V b Vin = 600 V 130 & The Institution of Engineering and Technology 2013

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