ZVS Class D Series Resonant Inverter-discrete-time ... - IEEE Xplore

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 11, NOVEMBER 1998

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ZVS Class D Series Resonant Inverter—Discrete-Time State-Space Simulation and Experimental Results Dariusz Czarkowski, Member, IEEE, and Marian K. Kazimierczuk, Senior Member, IEEE

Abstract— A numerical analysis of a Class D zero-voltage switching (ZVS) inverter in the time domain is presented along with experimental results. A discrete-time state-space approach is used for simulation. The state-space description and simulation results provide a fast insight into the physical operation of the converter. The algorithm is fast, easy to implement, and suitable for systems with high spikes in the waveforms and variable inputs. The analysis shows that switching losses can be reduced by using a dead time in the transistor drive voltages and adding a single capacitor in parallel with one of the transistors. ZVS can be achieved above the resonant frequency and in a limited range of the load resistance. The numerical results are in good agreement with the experimental ones. Index Terms— Resonant converters, series resonant inverter, simulation, zero-voltage switching.

I. INTRODUCTION

T

HE efficiency of Class D voltage-switching inverters [1], [2] is low at high frequencies due to switching losses [3], [4]. To reduce switching losses, zero-voltage switching (ZVS), or soft-switching, techniques have been applied [5]–[9]. ZVS can be achieved if the following conditions are satisfied. 1) A shunt capacitor in parallel with each of the transistors [5]–[8] or a single capacitor in parallel with one of the transistors [9] is added. 2) A dead time is present in waveforms of the drive voltages of the transistors. 3) The load of inverter switches is inductive. 4) The magnitude of the inductor current at the switch turnoff is sufficiently high to recharge the shunt capacitor. The purpose of this paper is to present a numerical analysis of a Class D ZVS inverter with one shunt capacitor [9], [10] in the time domain and validate this analysis with experimental results. Experimental waveforms are given for the inverter with and without shunt capacitor, and differences in the waveforms are discussed. A discrete-time state-space approach is used in the simulation. The mathematical description of the circuit and the computational algorithm given in this paper are based on the Manuscript received October 7, 1996; revised March 18, 1997. This paper was recommended by Associate Editor A. Ioinovici. D. Czarkowski is with the Department of Electrical Engineering, Polytechnic University, Brooklyn, NY 11201 USA. M. K. Kazimierczuk is with the Department of Electrical Engineering, Wright State University, Dayton, OH 45435 USA. Publisher Item Identifier S 1057-7122(98)07716-2.

ideas introduced in the fundamental and excellent work by Liou [11]. Many other successful approaches to simulation of analog-switched networks have been proposed, for instance, [12]–[16]. Detailed studies on problems associated with initial conditions and Dirac impulses in switched networks with ideal switches have been conducted [17]–[20]. The proposed methods focus on accuracy and generality. They provide means for simulation of networks with complicated topologies and a priori unknown switching instants. However, the general methods require a considerable effort in programming that often calls for an application of symbolic computational packages. On the other hand, using preprogrammed simulation tools, it is easy to lose physical insight into operation of a switched network. This paper shows that a discrete-time state-space approach has important advantages when applied by an experienced engineer to a design of a network with a simple topology. First, it allows the designer a fast check of a network’s selected feature. In this example, this feature is a zero-voltage-switching condition. Second, the state-space description enables the understanding of certain topological properties of the simulated circuit. For the Class D ZVS series resonant inverter, it is the equivalency of a single shunt capacitor to two shunt capacitors for the ac component.

II. PRINCIPLE

OF

OPERATION

A circuit of an improved Class D ZVS inverter [9] is shown and in Fig. 1(a). It consists of two bidirectional switches , a series-resonant circuit , and a shunt capacitor . and are comprised of power MOSFET’s The switches and and antiparallel diodes and . Other switching devices can also be used (MCT’s, BJT’s, IGBT’s). The dc represents a short circuit for the ac current. voltage source Therefore, the parasitic capacitances of both switches are for the ac component. Thus, connected in parallel with a single capacitor in parallel with one of the transistors allows for achieving the same result as two shunt capacitors, each in parallel with one transistor. The switches are driven alternately by the rectangular voltand with a sufficiently long dead time, i.e., the ON ages duty cycle of each drive voltage is less than 0.5. The switching must be higher than the resonant frequency frequency to achieve ZVS operation. For a sufficiently (e.g., and the high loaded quality factor

1057–7122/98$10.00  1998 IEEE

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where vector,

is the state vector, is the input is the constant state matrix, and is the constant input matrix. When the continuous system is uniformly sampled, the sequence of solutions at the sampling instants takes on the form for

(a)

(b) Fig. 1. Class D ZVS inverter: (a) circuit and (b) model.

switching frequency close enough to the resonant frequency, the series-resonant circuit forces a sinusoidal current . is ON, transistor and For steady state, when transistor both diodes are OFF, the voltage across the upper switch is nearly zero, and the voltage across the bottom switch is approximately equal to . When transistor is turned off all other semiconductor devices are by the driving voltage is OFF still OFF. Diodes are reverse biased and transistor due to the dead time ( is still low). The current is diverted to the shunt capacitor . For higher than from transistor , the current through capacitor is negative and discharges gradually decreases from the capacitor. The voltage to about V. The decrease in the voltage causes the . The current through increase of the voltage falls rapidly to zero while the voltage across transistor this transistor remains close to zero. Since the voltage and do not overlap, the turn-off current waveforms of transistor is approximately zero. switching loss in transistor reaches 0.7 V, diode turns on When the voltage is diverted to diode . During and the inductor current is ON, transistor is turned the time interval when diode increases from approximately 1 to on and the voltage 0.3 V, causing diode to turn off. All the diode reverserecovery current flows only through the transistor . Since is kept low, the turn-off switching loss of the voltage the diode and the turn-on switching loss of the transistor are nearly zero. Because of the symmetrical structure of the circuit for the ac components, the switching losses during the next and the turn-off transition, i.e., the turn-on loss in switch loss in switch , are also eliminated. III. MODEL

OF THE INVERTER

Every linear time-invariant system can be described by a continuous-time state equation (1)

(2)

and for a where nonsingular . Equation (2) allows for almost exact simulation of a continuous-time system in an iterative way [14]. A piecewise linear model of the Class D inverter of Fig. 1(a) is depicted in Fig. 1(b). The switches are modeled by periodically changing resistors in parallel with output capacitances is OFF, the value of of transistors. Thus, when the switch is and when the switch is ON, the value of is . It is assumed that both switches are identical. Therefore, depend on the state of the switch in an the values of depend on the state of the analogous way as the values represents the output capacitance switch . The capacitor of the switch , which is assumed to be linear. Capacitance consists of the output capacitance of switch (which is . The assumed to be linear) and the external capacitance circuit of Fig. 1(b) can be described by the state equation of the form given by (1), where

(3)

. Note that capacitances and and always occur as the sum . That means that they are topologically equivalent to one capacitance connected in parallel with one of the transistors.

IV. ALGORITHM In general, switched electronic circuits are nonlinear systems. But their high nonlinearity is only due to periodic changes in the circuit structure caused by the operation of the switches. Between switching instants, such an electronic circuit can be represented as a linear electric network. In every cycle of the switching frequency, the switched electronic circuit goes through a number of linear configurations. If the voltages across capacitors and the currents in inductors are selected as the state variables, each configuration is described by (1). For digital simulation purposes, it is very convenient to use the discrete-time model given by (2). For a circuit with nonideal switches, the physical property of the state variables is their continuity. Therefore, the initial conditions of each configuration are the final values of the state variables from the earlier configuration. The conditions for switching instants are determined by the drive signals of the controllable switches or by the natural commutation of the switches.

CZARKOWSKI AND KAZIMIERCZUK: ZVS CLASS D SERIES RESONANT INVERTER

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The steps of simulation are as follows. and the symbolic 1) Build the symbolic state matrix input matrix . and for each 2) Calculate the numerical forms of linear configuration. for each linear configuration. 3) Calculate and 4) Describe conditions for selection of a linear configuration used for calculations at each step. 5) Determine initial conditions for the first configuration. 6) Start simulation. (a)

V. NUMERICAL ANALYSIS OF CLASS D INVERTER In each cycle of operation, the ZVS Class D inverter, depicted in Fig. 1(a), goes through several configurations. Their number and sequence depend on the operating conditions. For the model of Fig. 1(b), these configurations are and ; 1) and ; 2) and . 3) and/or diode The first configuration occurs when transistor is ON. The second configuration corresponds to the situation when both switches are OFF. The third configuration and/or diode is ON. Using (2) as occurs when transistor a simulation equation, each configuration must be described and , where 1, 2, and 3. The by a pair of matrices V, circuit parameters of the simulated inverter are: , M , nF, nF, , H, nF, and the switching kHz. Hence, the resonant frequency is frequency kHz and the frequency ratio is . The ns. time step was Fig. 2 shows steady-state simulated waveforms of the voltacross capacitor and the current through age when the dead time is zero and . In resistor this case, the duty cycle of each switch is 0.5 and the circuit goes only through the first and the third of the configurations. Consequently, the switches are never simultaneously OFF or ON. Similar waveforms, but shifted by a half of the switching and resistor . period, are obtained for the capacitor The switch current waveform contains high spikes with a A. These positive spikes cause the magnitude of transistor switching losses and do not affect the rest of the can be circuit. Hence, the switching losses in transistor expressed as

(b) Fig. 2. Waveforms of the capacitor voltage vC 2 and the switch resistor current iR2 for the dead time equal to zero and R = 120 : (a) waveform of vC 2 and (b) waveform of iR2 .

resonant circuit is

(5) where (6) and (7) Assuming that the current discharging the capacitor is , the minimum dead time is constant and equal to

(4) is the voltage across capacitor at turn-on. In the where actual circuit, the current spikes may not be present because a MOSFET transistor behaves rather like a current source and not like a step changed resistor during switching action. The switching losses can be reduced by introducing a dead time into the switch driving voltages [5]–[9]. One of the tasks is to calculate the maximum allowable value of the dead time at full load. This value is determined by the time instant when the current through the series-resonant circuit crosses zero from negative to positive values. The input impedance of the

(8)

is the amplitude of the current where . Note that through the resonant circuit and the minimum dead time is independent of the dc input voltage . Fig. 3(a) shows the normalized minimum dead time

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(a)

(a)

(b) Fig. 4. Waveforms of the capacitor voltage vC 2 and the switch resistor current iR2 for the dead time equal to 882 ns and R = 120 : (a) waveform of vC 2 and (b) waveform of iR2 .

(b) Fig. 3. Normalized minimum and maximum dead times as functions of

fs =fr at various normalized load resistances R=Zo : (a) tDmin =(Ceq Zo ) and (b) tDmax fr .

versus the frequency ratio at various It can be seen that the values of the normalized load at light loads and minimum dead time decreases with at heavy initially decreases and then increases with loads. , the maximum value of the dead time Since obtained from (7) is

(9) ns. For the full load, the maximum dead time is Fig. 3(b) shows the normalized maximum dead time versus at various normalized loads . It can be increases with and decreases with seen that . the normalized load Fig. 4 shows waveforms of the voltage across capacitor and the current through resistor at the full load resistance and the maximum dead time ns. The is greater than because the values of value of

and are not taken into account in (9). One can observe that the switch current does not contain positive spikes which correspond to switching losses. The negative current spikes are only due to the discrete method of simulation and can be reduced to any value by applying a smaller sampling period They are not present in the actual circuit. Fig. 5 shows the waveforms of the voltage across capacitor and the current through resistor when the dead time and is 1134 ns. Between a period exceeds the value of and a when the negative current is conducted by diode period when the positive current is conducted by transistor , there is a period when both devices are OFF. The computer program simulates this situation by switching the abovementioned circuit configurations from the third configuration to the second one and again to the third. During the second and the current through is configuration, occurs at almost equal to zero. The turn-on of transistor nonzero voltage across capacitor . The switching losses are represented in Fig. 4(b) by positive current spikes of 42 A amplitude (not fully shown because of the figure scale). to Increasing the load resistance from at the fixed dead time ns, one obtains similar waveforms to those of Fig. 4. The absence of positive current spikes means that the circuit operates without switching losses. Fig. 6 depicts the waveforms of the voltage and the current through resistor when across capacitor and is 300 . One the load resistance is greater than can observe the positive current spikes representing switching losses. The dead time becomes too small to allow the voltage to fall to zero. This is because the across the capacitance


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(a)

(a)

(b)

(b)

Fig. 5. Waveforms of the capacitor voltage vC 2 and the switch resistor current iR2 for the dead time equal to 1134 ns and R = 120 : (a) waveform of vC 2 and (b) waveform of iR2 .

Fig. 6. Waveforms of the capacitor voltage vC 2 and the switch resistor current iR2 for the dead time equal to 882 ns and R = 300 : (a) waveform of vC 2 and (b) waveform of iR2 .

current charging the capacitance is low for a high load resistance. and a given minimum For a fixed switching frequency , the above procedure leads to estimation load resistance of a maximum allowable dead time and a range of the load resistance when the Class D inverter operates with no switching losses. Using the discrete-time modeling technique, one can investigate effects of other circuit parameters on will increase switching losses. An increase in ratio the maximum allowable dead time because it increases the phase shift between the resonant circuit voltage and current will not affect the maximum according to (9). A change in dead time since it does not change the time instant when the resonant current crosses zero.

switch for one cycle. It can be seen that the drain-to-source was approximately rectangular for voltage waveform and trapezoidal for nF. Fig. 7(b) shows the waveforms at the turn-on transition of in the enlarged scale. In both cases, the wavethe switch forms of the switch current and voltage were nonoverlapping, resulting in zero turn-on switching loss. Fig. 7(c) displays the waveforms at the turn-off transition of the switch . In the inverter without the shunt capacitor, the switch voltage had begun to increase before the switch current reached zero. On the other hand, in the inverter with the shunt capacitor, the switch current and voltage waveforms did not overlap. As a result, the turn-off switching loss was zero. VII. CONCLUSIONS

VI. EXPERIMENTAL RESULTS The inverter circuit of Fig. 1(a) was built and tested, using and , Motorola MTP5N40 MOSFET’s as switches H, resonant capacitor resonant inductor nF, nF, , and a Unitrode UC 2525 driver of the power MOSFET’s. The dc input voltage was V, the resonant frequency was 108 kHz, and the switching frequency was 119 kHz. The aforementioned components and correspond to the characteristic impedance . The measured output the loaded quality factor power was 50 W. Fig. 7 shows experimental current and voltage waveforms of the bottom switch without shunt capacitor and with shunt nF. Fig. 7(a) shows the waveforms of switch capacitor and drain-to-source voltage of the bottom current

A Class D ZVS inverter with a single shunt capacitor has been simulated using a discrete-time state-space method and experimentally verified. The simulation method is capable of analyzing circuits that generate high current (or voltage) spikes. The algorithm is easy to implement and control using software for matrix computations, e.g., MATLAB. Since it is fast, it allows for efficient interactive mode of operation. The state-space description gives a good insight into topological properties of a simulated circuit. The major drawback of the state-space method is the necessity to formulate a statespace description for each topological mode of the simulated circuit. The tradeoff among speed, accuracy, and memory requirements is of lesser importance with continuous advances in computer technology. The state-space discrete-time method can be a powerful simulation and analysis tool when applied

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(a)

(b)

(c) Fig. 7. Waveforms of the bottom transistor without shunt capacitor (left column) and with shunt capacitor Cs = 1 nF (right column). (a) Waveforms of vGS 2 (5 V/div.), iS2 (1 A/div.), and vDS2 (100 V/div.); horizontal: 1 s/div. (b) Waveforms of iS2 (0.2 A/div.) and vDS2 (50 V/div.) at turn-on of switch S 2; horizontal: 0.1 s/div. (c) Waveforms of iS2 (0.2 A/div.) and vDS2 (50 V/div.) at turn-off of switch S 2; horizontal: 0.1 s/div.

by an experienced engineer to not overly complicated powerconverter topology. The discrete-time simulation of the ZVS series resonant inverter has confirmed that it is possible to eliminate switching losses by using a shunt capacitor and a dead time. It follows from the state-space equations that the shunt capacitor can be connected in parallel with one of the switches or divided into two capacitors. Therefore, it suffices to use only one shunt capacitor in a practical circuit. ZVS can be achieved in a limited range of load resistances. At light loads, the amplitude of the current through the resonant circuit is low. As a result, recharging of the shunt capacitor becomes slow and the dead time is too short to reduce the switch voltage to zero. On the other hand, the dead time cannot be too long because the transistor should be turned on when the switch current is negative. Two Class D inverters were built: one without the shunt capacitor and the other with the shunt capacitor. The current and voltage waveforms of the bottom switch were observed

and compared. In the circuit without the shunt capacitor, the switch current and voltage waveforms were simultaneously nonzero during the turn-off transition, causing switching loss. In contrast, in the inverter with the shunt capacitor, the switch current and voltage waveforms were displaced with respect of time, yielding zero switching loss. In the inverter with a series-resonant circuit, the magnitude of the inductor current decreases with the load resistance. For this reason, the load range in which ZVS operation is achievable is narrow. However, this drawback does not exist in an inverter in which the load is connected in parallel with the resonant capacitor, e.g., in parallel resonant inverter [21]. An analysis of such circuits is recommended for further research. REFERENCES [1] P. J. Baxandall, “Transistor sine-wave LC oscillators, some general considerations and new developments,” Proc. Inst. Electr. Eng., vol. 106, pp. 748–758, pt. B, suppl. 16, May 1959. [2] M. R. Osborne, “Design of tuned transistor power amplifier,” Electron. Eng., vol. 40, no. 486, pp. 436–443, 1968.


[3] W. J. Chudobiak and D. F. Page, “Frequency and power limitations of Class-D transistor amplifier,” IEEE J. Solid-State Circuits, vol. SC-4, pp. 25–37, Feb. 1969. [4] M. Kazimierczuk, “Class D voltage-switching MOSFET amplifier,” Proc. Inst. Electr. Eng., vol. 138, pp. 285–296, pt. B, Nov. 1991. [5] H. Foch and J. Roux, “Static semiconductor electrical energy converter,” U.S. Patent 4 330 819, May 18, 1982. [6] B. Carsten, “Fast, accurate measurement of core loss at high frequencies,” Powerconv. and Intell. Motion, vol. 12, pp. 29–33, Mar. 1986. , “A hybrid series-parallel converter for high frequencies and [7] power levels,” in Proc. High Frequency Power Conversion Conf., Washington, DC, Apr. 1987, pp. 41–47. [8] F. M. Magalhaes, F. T. Dickens, G. R. Westerman, and N. G. Ziesse, “Zero-voltage-switched resonant half-bridge high-voltage dc–dc converter,” in Proc. High Frequency Power Conversion Conf., San Diego, CA, May 1–5, 1988, pp. 332–343. [9] M. K. Kazimierczuk and W. Szaraniec, “Class D zero-voltage-switching inverter with only one shunt capacitor,” Proc. Inst. Electr. Eng., vol. 139, pp. 449–456, pt. B, Oct. 1992. [10] M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters. New York: Wiley Interscience, 1995. [11] M. Liou, “Exact analysis of linear circuits containing periodically operated switches with applications,” IEEE Trans. Circuit Theory, vol. CT-19, pp. 146–154, Mar. 1972. [12] C. Liu, C. H. K. Chang, Y. Hsiao, and J. M. Bocek, “A fast-decoupled method for time-domain simulation of power converters,” in Proc. IEEE Power Electron. Specialists Conf., Apr. 1988, pp. 748–755. [13] A. Shenkman and A. Ioinovici, “General algorithm for computer-aided transient and steady-state analysis of dc to dc converters,” Int. J. Syst. Sci., vol. 20, no. 10, pp. 1955–1966, Oct. 1989. [14] A. M. Luciano and A. G. M. Strollo, “A fast time-domain algorithm for the simulation of switching power converters,” IEEE Trans. Power Electron., vol. 5, pp. 363–370, July 1990. [15] D. Bedrosian and J. Vlach, “Time-domain analysis of networks with internally controlled switches,” IEEE Trans. Circuits Syst. I, vol. 39, pp. 199–212, Mar. 1992. [16] H. S.-H. Chung and A. Ioinovici, “Fast computer-aided simulation of switching power regulators based on progressive analysis of the switches’ state,” IEEE Trans. Power Electron., vol. 9, pp. 206–212, Mar. 1994. [17] A. Opal and J. Vlach, “Consistent initial conditions of linear switched networks,” IEEE Trans. Circuits Syst., vol. 37, pp. 364–372, Mar. 1990. , “Consistent initial conditions of nonlinear networks with [18] switches,” IEEE Trans. Circuits Syst., vol. 38, no. 7, pp. 698–710, July 1991. [19] J. Vlach, J. M. Wojciechowski, and A. Opal, “Analysis of nonlinear networks with inconsistent initial conditions,” IEEE Trans. Circuits Syst., I, vol. 42, pp. 195–199, Apr. 1995. [20] A. Massarini and M. K. Kazimierczuk, “A new representation of Dirac impulses in time-domain computer analysis of networks with ideal switches,” in IEEE Int. Symp. Circuits and Systems, Atlanta, GA, May 12–15, 1996, pp. 565–568. [21] M. K. Kazimierczuk, W. Szaraniec, and S. Wang, “Analysis and design of parallel resonant converter at high QL ;” IEEE Trans. Aerosp. Electron. Syst., vol. AES-28, no. 1, pp. 35–50, Jan. 1992.

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Dariusz Czarkowski (M’97) received the M.S. degree in electronics engineering from the University of Mining and Metallurgy, Cracow, Poland, and the M.S.Egr. degree in electrical engineering from Wright State University, Dayton, OH, in 1989 and 1993, respectively. He received the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, in 1996. He joined the Polytechnic University, Brooklyn, NY, as an Assistant Professor of Electrical Engineering in 1996. His research interests are in the areas of power converters, electric drives, power quality, and modern power devices. He coauthored (with M. K. Kazimierczuk) Resonant Power Converters (Wiley Interscience, 1995). He has published more than 30 technical papers and articles in IEEE journals and conference proceedings. Dr. Czarkowski is a member of Sigma Xi and Eta Kappa Nu.

Marian K. Kazimierczuk (M’91–SM’91) received the M.S., Ph.D., and D.Sci. degrees in electronics engineering from the Department of Electronics, Technical University of Warsaw, Warsaw, Poland, in 1971, 1978, and 1984, respectively. He was a Teaching and Research Assistant from 1972 to 1978 and Assistant Professor from 1978 to 1984 with the Department of Electronics, Institute of Radio Electronics, Technical University of Warsaw, Poland. In 1984, he was a Project Engineer for Design Automation, Inc., Lexington, MA. In 1984–1985, he was a Visiting Professor with the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, VA. Since 1985, he has been with the Department of Electrical Engineering, Wright State University, Dayton, OH, where he is currently a Professor. His research interests are in resonant and PWM dc/dc power converters, dc/ac inverters, high-frequency rectifiers, electronic ballasts, magnetics, power semiconductor devices, and high-frequency high-efficiency power tuned amplifiers. He is a co-author of the book Resonant Power Converters (Wiley Interscience, 1995). He has published more than 200 technical papers, more than 70 of which have appeared in IEEE TRANSACTIONS and Journals. In 1991, Dr. Kazimierczuk received the IEEE Harrell V. Noble Award for his contributions to the fields of aerospace, industrial, and power electronics. He is also a recipient of the 1991 Presidential Award for Faculty Excellence in Research, the 1993 College Teaching Award, the 1995 Presidential Award for Outstanding Faculty Member, and Brage Golding Distinguished Professor of Research Award from Wright State University. He has been an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I and serves as an Associate Editor for the Journal of Circuits, Systems, and Computers. He is a member of the Superconductivity Committee of the IEEE Power Electronics Society and a member of Tau Beta Pi.